1 /* 2 * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/debug.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/clk.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <drivers/st/stm32mp_clkfunc.h> 20 #include <drivers/st/stm32mp1_clk.h> 21 #include <drivers/st/stm32mp1_rcc.h> 22 #include <dt-bindings/clock/stm32mp1-clksrc.h> 23 #include <lib/mmio.h> 24 #include <lib/spinlock.h> 25 #include <lib/utils_def.h> 26 #include <libfdt.h> 27 #include <plat/common/platform.h> 28 29 #include <platform_def.h> 30 31 #define MAX_HSI_HZ 64000000 32 #define USB_PHY_48_MHZ 48000000 33 34 #define TIMEOUT_US_200MS U(200000) 35 #define TIMEOUT_US_1S U(1000000) 36 37 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 38 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 39 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 40 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 41 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 42 43 const char *stm32mp_osc_node_label[NB_OSC] = { 44 [_LSI] = "clk-lsi", 45 [_LSE] = "clk-lse", 46 [_HSI] = "clk-hsi", 47 [_HSE] = "clk-hse", 48 [_CSI] = "clk-csi", 49 [_I2S_CKIN] = "i2s_ckin", 50 }; 51 52 enum stm32mp1_parent_id { 53 /* Oscillators are defined in enum stm32mp_osc_id */ 54 55 /* Other parent source */ 56 _HSI_KER = NB_OSC, 57 _HSE_KER, 58 _HSE_KER_DIV2, 59 _HSE_RTC, 60 _CSI_KER, 61 _PLL1_P, 62 _PLL1_Q, 63 _PLL1_R, 64 _PLL2_P, 65 _PLL2_Q, 66 _PLL2_R, 67 _PLL3_P, 68 _PLL3_Q, 69 _PLL3_R, 70 _PLL4_P, 71 _PLL4_Q, 72 _PLL4_R, 73 _ACLK, 74 _PCLK1, 75 _PCLK2, 76 _PCLK3, 77 _PCLK4, 78 _PCLK5, 79 _HCLK6, 80 _HCLK2, 81 _CK_PER, 82 _CK_MPU, 83 _CK_MCU, 84 _USB_PHY_48, 85 _PARENT_NB, 86 _UNKNOWN_ID = 0xff, 87 }; 88 89 /* Lists only the parent clock we are interested in */ 90 enum stm32mp1_parent_sel { 91 _I2C12_SEL, 92 _I2C35_SEL, 93 _STGEN_SEL, 94 _I2C46_SEL, 95 _SPI6_SEL, 96 _UART1_SEL, 97 _RNG1_SEL, 98 _UART6_SEL, 99 _UART24_SEL, 100 _UART35_SEL, 101 _UART78_SEL, 102 _SDMMC12_SEL, 103 _SDMMC3_SEL, 104 _QSPI_SEL, 105 _FMC_SEL, 106 _AXIS_SEL, 107 _MCUS_SEL, 108 _USBPHY_SEL, 109 _USBO_SEL, 110 _MPU_SEL, 111 _CKPER_SEL, 112 _RTC_SEL, 113 _PARENT_SEL_NB, 114 _UNKNOWN_SEL = 0xff, 115 }; 116 117 /* State the parent clock ID straight related to a clock */ 118 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 119 [_HSE] = CK_HSE, 120 [_HSI] = CK_HSI, 121 [_CSI] = CK_CSI, 122 [_LSE] = CK_LSE, 123 [_LSI] = CK_LSI, 124 [_I2S_CKIN] = _UNKNOWN_ID, 125 [_USB_PHY_48] = _UNKNOWN_ID, 126 [_HSI_KER] = CK_HSI, 127 [_HSE_KER] = CK_HSE, 128 [_HSE_KER_DIV2] = CK_HSE_DIV2, 129 [_HSE_RTC] = _UNKNOWN_ID, 130 [_CSI_KER] = CK_CSI, 131 [_PLL1_P] = PLL1_P, 132 [_PLL1_Q] = PLL1_Q, 133 [_PLL1_R] = PLL1_R, 134 [_PLL2_P] = PLL2_P, 135 [_PLL2_Q] = PLL2_Q, 136 [_PLL2_R] = PLL2_R, 137 [_PLL3_P] = PLL3_P, 138 [_PLL3_Q] = PLL3_Q, 139 [_PLL3_R] = PLL3_R, 140 [_PLL4_P] = PLL4_P, 141 [_PLL4_Q] = PLL4_Q, 142 [_PLL4_R] = PLL4_R, 143 [_ACLK] = CK_AXI, 144 [_PCLK1] = CK_AXI, 145 [_PCLK2] = CK_AXI, 146 [_PCLK3] = CK_AXI, 147 [_PCLK4] = CK_AXI, 148 [_PCLK5] = CK_AXI, 149 [_CK_PER] = CK_PER, 150 [_CK_MPU] = CK_MPU, 151 [_CK_MCU] = CK_MCU, 152 }; 153 154 static unsigned int clock_id2parent_id(unsigned long id) 155 { 156 unsigned int n; 157 158 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 159 if (parent_id_clock_id[n] == id) { 160 return n; 161 } 162 } 163 164 return _UNKNOWN_ID; 165 } 166 167 enum stm32mp1_pll_id { 168 _PLL1, 169 _PLL2, 170 _PLL3, 171 _PLL4, 172 _PLL_NB 173 }; 174 175 enum stm32mp1_div_id { 176 _DIV_P, 177 _DIV_Q, 178 _DIV_R, 179 _DIV_NB, 180 }; 181 182 enum stm32mp1_clksrc_id { 183 CLKSRC_MPU, 184 CLKSRC_AXI, 185 CLKSRC_MCU, 186 CLKSRC_PLL12, 187 CLKSRC_PLL3, 188 CLKSRC_PLL4, 189 CLKSRC_RTC, 190 CLKSRC_MCO1, 191 CLKSRC_MCO2, 192 CLKSRC_NB 193 }; 194 195 enum stm32mp1_clkdiv_id { 196 CLKDIV_MPU, 197 CLKDIV_AXI, 198 CLKDIV_MCU, 199 CLKDIV_APB1, 200 CLKDIV_APB2, 201 CLKDIV_APB3, 202 CLKDIV_APB4, 203 CLKDIV_APB5, 204 CLKDIV_RTC, 205 CLKDIV_MCO1, 206 CLKDIV_MCO2, 207 CLKDIV_NB 208 }; 209 210 enum stm32mp1_pllcfg { 211 PLLCFG_M, 212 PLLCFG_N, 213 PLLCFG_P, 214 PLLCFG_Q, 215 PLLCFG_R, 216 PLLCFG_O, 217 PLLCFG_NB 218 }; 219 220 enum stm32mp1_pllcsg { 221 PLLCSG_MOD_PER, 222 PLLCSG_INC_STEP, 223 PLLCSG_SSCG_MODE, 224 PLLCSG_NB 225 }; 226 227 enum stm32mp1_plltype { 228 PLL_800, 229 PLL_1600, 230 PLL_TYPE_NB 231 }; 232 233 struct stm32mp1_pll { 234 uint8_t refclk_min; 235 uint8_t refclk_max; 236 uint8_t divn_max; 237 }; 238 239 struct stm32mp1_clk_gate { 240 uint16_t offset; 241 uint8_t bit; 242 uint8_t index; 243 uint8_t set_clr; 244 uint8_t secure; 245 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 246 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 247 }; 248 249 struct stm32mp1_clk_sel { 250 uint16_t offset; 251 uint8_t src; 252 uint8_t msk; 253 uint8_t nb_parent; 254 const uint8_t *parent; 255 }; 256 257 #define REFCLK_SIZE 4 258 struct stm32mp1_clk_pll { 259 enum stm32mp1_plltype plltype; 260 uint16_t rckxselr; 261 uint16_t pllxcfgr1; 262 uint16_t pllxcfgr2; 263 uint16_t pllxfracr; 264 uint16_t pllxcr; 265 uint16_t pllxcsgr; 266 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 267 }; 268 269 /* Clocks with selectable source and non set/clr register access */ 270 #define _CLK_SELEC(sec, off, b, idx, s) \ 271 { \ 272 .offset = (off), \ 273 .bit = (b), \ 274 .index = (idx), \ 275 .set_clr = 0, \ 276 .secure = (sec), \ 277 .sel = (s), \ 278 .fixed = _UNKNOWN_ID, \ 279 } 280 281 /* Clocks with fixed source and non set/clr register access */ 282 #define _CLK_FIXED(sec, off, b, idx, f) \ 283 { \ 284 .offset = (off), \ 285 .bit = (b), \ 286 .index = (idx), \ 287 .set_clr = 0, \ 288 .secure = (sec), \ 289 .sel = _UNKNOWN_SEL, \ 290 .fixed = (f), \ 291 } 292 293 /* Clocks with selectable source and set/clr register access */ 294 #define _CLK_SC_SELEC(sec, off, b, idx, s) \ 295 { \ 296 .offset = (off), \ 297 .bit = (b), \ 298 .index = (idx), \ 299 .set_clr = 1, \ 300 .secure = (sec), \ 301 .sel = (s), \ 302 .fixed = _UNKNOWN_ID, \ 303 } 304 305 /* Clocks with fixed source and set/clr register access */ 306 #define _CLK_SC_FIXED(sec, off, b, idx, f) \ 307 { \ 308 .offset = (off), \ 309 .bit = (b), \ 310 .index = (idx), \ 311 .set_clr = 1, \ 312 .secure = (sec), \ 313 .sel = _UNKNOWN_SEL, \ 314 .fixed = (f), \ 315 } 316 317 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 318 [_ ## _label ## _SEL] = { \ 319 .offset = _rcc_selr, \ 320 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 321 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 322 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 323 .parent = (_parents), \ 324 .nb_parent = ARRAY_SIZE(_parents) \ 325 } 326 327 #define _CLK_PLL(idx, type, off1, off2, off3, \ 328 off4, off5, off6, \ 329 p1, p2, p3, p4) \ 330 [(idx)] = { \ 331 .plltype = (type), \ 332 .rckxselr = (off1), \ 333 .pllxcfgr1 = (off2), \ 334 .pllxcfgr2 = (off3), \ 335 .pllxfracr = (off4), \ 336 .pllxcr = (off5), \ 337 .pllxcsgr = (off6), \ 338 .refclk[0] = (p1), \ 339 .refclk[1] = (p2), \ 340 .refclk[2] = (p3), \ 341 .refclk[3] = (p4), \ 342 } 343 344 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 345 346 #define SEC 1 347 #define N_S 0 348 349 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 350 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 351 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 352 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 353 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 354 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 355 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 356 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 357 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 358 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 359 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 360 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 361 362 #if defined(IMAGE_BL32) 363 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 364 #endif 365 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 366 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 367 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 368 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 369 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 370 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 371 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 372 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 373 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 374 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 375 376 #if defined(IMAGE_BL32) 377 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 378 #endif 379 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 380 381 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 382 383 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 384 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 385 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 386 387 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 388 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 389 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 390 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 391 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 392 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 393 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 394 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 395 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 396 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 397 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 398 399 #if defined(IMAGE_BL32) 400 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 401 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 402 #endif 403 404 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 405 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 406 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 407 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 408 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 409 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 410 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 411 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 412 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 413 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 414 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 415 416 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 417 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 418 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 419 _CLK_SC_SELEC(SEC, RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 420 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 421 422 #if defined(IMAGE_BL2) 423 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 424 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 425 #endif 426 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 427 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 428 #if defined(IMAGE_BL32) 429 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 430 #endif 431 432 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL), 433 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 434 }; 435 436 static const uint8_t i2c12_parents[] = { 437 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 438 }; 439 440 static const uint8_t i2c35_parents[] = { 441 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 442 }; 443 444 static const uint8_t stgen_parents[] = { 445 _HSI_KER, _HSE_KER 446 }; 447 448 static const uint8_t i2c46_parents[] = { 449 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 450 }; 451 452 static const uint8_t spi6_parents[] = { 453 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 454 }; 455 456 static const uint8_t usart1_parents[] = { 457 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 458 }; 459 460 static const uint8_t rng1_parents[] = { 461 _CSI, _PLL4_R, _LSE, _LSI 462 }; 463 464 static const uint8_t uart6_parents[] = { 465 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 466 }; 467 468 static const uint8_t uart234578_parents[] = { 469 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 470 }; 471 472 static const uint8_t sdmmc12_parents[] = { 473 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 474 }; 475 476 static const uint8_t sdmmc3_parents[] = { 477 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 478 }; 479 480 static const uint8_t qspi_parents[] = { 481 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 482 }; 483 484 static const uint8_t fmc_parents[] = { 485 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 486 }; 487 488 static const uint8_t axiss_parents[] = { 489 _HSI, _HSE, _PLL2_P 490 }; 491 492 static const uint8_t mcuss_parents[] = { 493 _HSI, _HSE, _CSI, _PLL3_P 494 }; 495 496 static const uint8_t usbphy_parents[] = { 497 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 498 }; 499 500 static const uint8_t usbo_parents[] = { 501 _PLL4_R, _USB_PHY_48 502 }; 503 504 static const uint8_t mpu_parents[] = { 505 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 506 }; 507 508 static const uint8_t per_parents[] = { 509 _HSI, _HSE, _CSI, 510 }; 511 512 static const uint8_t rtc_parents[] = { 513 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 514 }; 515 516 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 517 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 518 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 519 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 520 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 521 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 522 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 523 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 524 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 525 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents), 526 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 527 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 528 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 529 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 530 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 531 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 532 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 533 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 534 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 535 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents), 536 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents), 537 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 538 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 539 }; 540 541 /* Define characteristic of PLL according type */ 542 #define DIVN_MIN 24 543 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 544 [PLL_800] = { 545 .refclk_min = 4, 546 .refclk_max = 16, 547 .divn_max = 99, 548 }, 549 [PLL_1600] = { 550 .refclk_min = 8, 551 .refclk_max = 16, 552 .divn_max = 199, 553 }, 554 }; 555 556 /* PLLNCFGR2 register divider by output */ 557 static const uint8_t pllncfgr2[_DIV_NB] = { 558 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 559 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 560 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 561 }; 562 563 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 564 _CLK_PLL(_PLL1, PLL_1600, 565 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 566 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 567 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 568 _CLK_PLL(_PLL2, PLL_1600, 569 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 570 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 571 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 572 _CLK_PLL(_PLL3, PLL_800, 573 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 574 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 575 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 576 _CLK_PLL(_PLL4, PLL_800, 577 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 578 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 579 _HSI, _HSE, _CSI, _I2S_CKIN), 580 }; 581 582 /* Prescaler table lookups for clock computation */ 583 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 584 static const uint8_t stm32mp1_mcu_div[16] = { 585 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 586 }; 587 588 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 589 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 590 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 591 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 592 0, 1, 2, 3, 4, 4, 4, 4 593 }; 594 595 /* div = /1 /2 /3 /4 */ 596 static const uint8_t stm32mp1_axi_div[8] = { 597 1, 2, 3, 4, 4, 4, 4, 4 598 }; 599 600 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 601 [_HSI] = "HSI", 602 [_HSE] = "HSE", 603 [_CSI] = "CSI", 604 [_LSI] = "LSI", 605 [_LSE] = "LSE", 606 [_I2S_CKIN] = "I2S_CKIN", 607 [_HSI_KER] = "HSI_KER", 608 [_HSE_KER] = "HSE_KER", 609 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 610 [_HSE_RTC] = "HSE_RTC", 611 [_CSI_KER] = "CSI_KER", 612 [_PLL1_P] = "PLL1_P", 613 [_PLL1_Q] = "PLL1_Q", 614 [_PLL1_R] = "PLL1_R", 615 [_PLL2_P] = "PLL2_P", 616 [_PLL2_Q] = "PLL2_Q", 617 [_PLL2_R] = "PLL2_R", 618 [_PLL3_P] = "PLL3_P", 619 [_PLL3_Q] = "PLL3_Q", 620 [_PLL3_R] = "PLL3_R", 621 [_PLL4_P] = "PLL4_P", 622 [_PLL4_Q] = "PLL4_Q", 623 [_PLL4_R] = "PLL4_R", 624 [_ACLK] = "ACLK", 625 [_PCLK1] = "PCLK1", 626 [_PCLK2] = "PCLK2", 627 [_PCLK3] = "PCLK3", 628 [_PCLK4] = "PCLK4", 629 [_PCLK5] = "PCLK5", 630 [_HCLK6] = "KCLK6", 631 [_HCLK2] = "HCLK2", 632 [_CK_PER] = "CK_PER", 633 [_CK_MPU] = "CK_MPU", 634 [_CK_MCU] = "CK_MCU", 635 [_USB_PHY_48] = "USB_PHY_48", 636 }; 637 638 /* RCC clock device driver private */ 639 static unsigned long stm32mp1_osc[NB_OSC]; 640 static struct spinlock reg_lock; 641 static unsigned int gate_refcounts[NB_GATES]; 642 static struct spinlock refcount_lock; 643 644 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 645 { 646 return &stm32mp1_clk_gate[idx]; 647 } 648 649 #if defined(IMAGE_BL32) 650 static bool gate_is_non_secure(const struct stm32mp1_clk_gate *gate) 651 { 652 return gate->secure == N_S; 653 } 654 #endif 655 656 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 657 { 658 return &stm32mp1_clk_sel[idx]; 659 } 660 661 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 662 { 663 return &stm32mp1_clk_pll[idx]; 664 } 665 666 static void stm32mp1_clk_lock(struct spinlock *lock) 667 { 668 if (stm32mp_lock_available()) { 669 /* Assume interrupts are masked */ 670 spin_lock(lock); 671 } 672 } 673 674 static void stm32mp1_clk_unlock(struct spinlock *lock) 675 { 676 if (stm32mp_lock_available()) { 677 spin_unlock(lock); 678 } 679 } 680 681 bool stm32mp1_rcc_is_secure(void) 682 { 683 uintptr_t rcc_base = stm32mp_rcc_base(); 684 uint32_t mask = RCC_TZCR_TZEN; 685 686 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 687 } 688 689 bool stm32mp1_rcc_is_mckprot(void) 690 { 691 uintptr_t rcc_base = stm32mp_rcc_base(); 692 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT; 693 694 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 695 } 696 697 void stm32mp1_clk_rcc_regs_lock(void) 698 { 699 stm32mp1_clk_lock(®_lock); 700 } 701 702 void stm32mp1_clk_rcc_regs_unlock(void) 703 { 704 stm32mp1_clk_unlock(®_lock); 705 } 706 707 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 708 { 709 if (idx >= NB_OSC) { 710 return 0; 711 } 712 713 return stm32mp1_osc[idx]; 714 } 715 716 static int stm32mp1_clk_get_gated_id(unsigned long id) 717 { 718 unsigned int i; 719 720 for (i = 0U; i < NB_GATES; i++) { 721 if (gate_ref(i)->index == id) { 722 return i; 723 } 724 } 725 726 ERROR("%s: clk id %lu not found\n", __func__, id); 727 728 return -EINVAL; 729 } 730 731 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 732 { 733 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 734 } 735 736 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 737 { 738 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 739 } 740 741 static int stm32mp1_clk_get_parent(unsigned long id) 742 { 743 const struct stm32mp1_clk_sel *sel; 744 uint32_t p_sel; 745 int i; 746 enum stm32mp1_parent_id p; 747 enum stm32mp1_parent_sel s; 748 uintptr_t rcc_base = stm32mp_rcc_base(); 749 750 /* Few non gateable clock have a static parent ID, find them */ 751 i = (int)clock_id2parent_id(id); 752 if (i != _UNKNOWN_ID) { 753 return i; 754 } 755 756 i = stm32mp1_clk_get_gated_id(id); 757 if (i < 0) { 758 panic(); 759 } 760 761 p = stm32mp1_clk_get_fixed_parent(i); 762 if (p < _PARENT_NB) { 763 return (int)p; 764 } 765 766 s = stm32mp1_clk_get_sel(i); 767 if (s == _UNKNOWN_SEL) { 768 return -EINVAL; 769 } 770 if (s >= _PARENT_SEL_NB) { 771 panic(); 772 } 773 774 sel = clk_sel_ref(s); 775 p_sel = (mmio_read_32(rcc_base + sel->offset) & 776 (sel->msk << sel->src)) >> sel->src; 777 if (p_sel < sel->nb_parent) { 778 return (int)sel->parent[p_sel]; 779 } 780 781 return -EINVAL; 782 } 783 784 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 785 { 786 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 787 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 788 789 return stm32mp1_clk_get_fixed(pll->refclk[src]); 790 } 791 792 /* 793 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 794 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 795 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 796 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 797 */ 798 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 799 { 800 unsigned long refclk, fvco; 801 uint32_t cfgr1, fracr, divm, divn; 802 uintptr_t rcc_base = stm32mp_rcc_base(); 803 804 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 805 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 806 807 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 808 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 809 810 refclk = stm32mp1_pll_get_fref(pll); 811 812 /* 813 * With FRACV : 814 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 815 * Without FRACV 816 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 817 */ 818 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 819 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 820 RCC_PLLNFRACR_FRACV_SHIFT; 821 unsigned long long numerator, denominator; 822 823 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 824 numerator = refclk * numerator; 825 denominator = ((unsigned long long)divm + 1U) << 13; 826 fvco = (unsigned long)(numerator / denominator); 827 } else { 828 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 829 } 830 831 return fvco; 832 } 833 834 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 835 enum stm32mp1_div_id div_id) 836 { 837 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 838 unsigned long dfout; 839 uint32_t cfgr2, divy; 840 841 if (div_id >= _DIV_NB) { 842 return 0; 843 } 844 845 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 846 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 847 848 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 849 850 return dfout; 851 } 852 853 static unsigned long get_clock_rate(int p) 854 { 855 uint32_t reg, clkdiv; 856 unsigned long clock = 0; 857 uintptr_t rcc_base = stm32mp_rcc_base(); 858 859 switch (p) { 860 case _CK_MPU: 861 /* MPU sub system */ 862 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 863 switch (reg & RCC_SELR_SRC_MASK) { 864 case RCC_MPCKSELR_HSI: 865 clock = stm32mp1_clk_get_fixed(_HSI); 866 break; 867 case RCC_MPCKSELR_HSE: 868 clock = stm32mp1_clk_get_fixed(_HSE); 869 break; 870 case RCC_MPCKSELR_PLL: 871 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 872 break; 873 case RCC_MPCKSELR_PLL_MPUDIV: 874 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 875 876 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 877 clkdiv = reg & RCC_MPUDIV_MASK; 878 clock >>= stm32mp1_mpu_div[clkdiv]; 879 break; 880 default: 881 break; 882 } 883 break; 884 /* AXI sub system */ 885 case _ACLK: 886 case _HCLK2: 887 case _HCLK6: 888 case _PCLK4: 889 case _PCLK5: 890 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 891 switch (reg & RCC_SELR_SRC_MASK) { 892 case RCC_ASSCKSELR_HSI: 893 clock = stm32mp1_clk_get_fixed(_HSI); 894 break; 895 case RCC_ASSCKSELR_HSE: 896 clock = stm32mp1_clk_get_fixed(_HSE); 897 break; 898 case RCC_ASSCKSELR_PLL: 899 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 900 break; 901 default: 902 break; 903 } 904 905 /* System clock divider */ 906 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 907 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 908 909 switch (p) { 910 case _PCLK4: 911 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 912 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 913 break; 914 case _PCLK5: 915 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 916 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 917 break; 918 default: 919 break; 920 } 921 break; 922 /* MCU sub system */ 923 case _CK_MCU: 924 case _PCLK1: 925 case _PCLK2: 926 case _PCLK3: 927 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 928 switch (reg & RCC_SELR_SRC_MASK) { 929 case RCC_MSSCKSELR_HSI: 930 clock = stm32mp1_clk_get_fixed(_HSI); 931 break; 932 case RCC_MSSCKSELR_HSE: 933 clock = stm32mp1_clk_get_fixed(_HSE); 934 break; 935 case RCC_MSSCKSELR_CSI: 936 clock = stm32mp1_clk_get_fixed(_CSI); 937 break; 938 case RCC_MSSCKSELR_PLL: 939 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 940 break; 941 default: 942 break; 943 } 944 945 /* MCU clock divider */ 946 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 947 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 948 949 switch (p) { 950 case _PCLK1: 951 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 952 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 953 break; 954 case _PCLK2: 955 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 956 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 957 break; 958 case _PCLK3: 959 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 960 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 961 break; 962 case _CK_MCU: 963 default: 964 break; 965 } 966 break; 967 case _CK_PER: 968 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 969 switch (reg & RCC_SELR_SRC_MASK) { 970 case RCC_CPERCKSELR_HSI: 971 clock = stm32mp1_clk_get_fixed(_HSI); 972 break; 973 case RCC_CPERCKSELR_HSE: 974 clock = stm32mp1_clk_get_fixed(_HSE); 975 break; 976 case RCC_CPERCKSELR_CSI: 977 clock = stm32mp1_clk_get_fixed(_CSI); 978 break; 979 default: 980 break; 981 } 982 break; 983 case _HSI: 984 case _HSI_KER: 985 clock = stm32mp1_clk_get_fixed(_HSI); 986 break; 987 case _CSI: 988 case _CSI_KER: 989 clock = stm32mp1_clk_get_fixed(_CSI); 990 break; 991 case _HSE: 992 case _HSE_KER: 993 clock = stm32mp1_clk_get_fixed(_HSE); 994 break; 995 case _HSE_KER_DIV2: 996 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 997 break; 998 case _HSE_RTC: 999 clock = stm32mp1_clk_get_fixed(_HSE); 1000 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U; 1001 break; 1002 case _LSI: 1003 clock = stm32mp1_clk_get_fixed(_LSI); 1004 break; 1005 case _LSE: 1006 clock = stm32mp1_clk_get_fixed(_LSE); 1007 break; 1008 /* PLL */ 1009 case _PLL1_P: 1010 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 1011 break; 1012 case _PLL1_Q: 1013 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 1014 break; 1015 case _PLL1_R: 1016 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 1017 break; 1018 case _PLL2_P: 1019 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 1020 break; 1021 case _PLL2_Q: 1022 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 1023 break; 1024 case _PLL2_R: 1025 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 1026 break; 1027 case _PLL3_P: 1028 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1029 break; 1030 case _PLL3_Q: 1031 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1032 break; 1033 case _PLL3_R: 1034 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1035 break; 1036 case _PLL4_P: 1037 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1038 break; 1039 case _PLL4_Q: 1040 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1041 break; 1042 case _PLL4_R: 1043 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1044 break; 1045 /* Other */ 1046 case _USB_PHY_48: 1047 clock = USB_PHY_48_MHZ; 1048 break; 1049 default: 1050 break; 1051 } 1052 1053 return clock; 1054 } 1055 1056 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1057 { 1058 uintptr_t rcc_base = stm32mp_rcc_base(); 1059 1060 VERBOSE("Enable clock %u\n", gate->index); 1061 1062 if (gate->set_clr != 0U) { 1063 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1064 } else { 1065 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1066 } 1067 } 1068 1069 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1070 { 1071 uintptr_t rcc_base = stm32mp_rcc_base(); 1072 1073 VERBOSE("Disable clock %u\n", gate->index); 1074 1075 if (gate->set_clr != 0U) { 1076 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1077 BIT(gate->bit)); 1078 } else { 1079 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1080 } 1081 } 1082 1083 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1084 { 1085 uintptr_t rcc_base = stm32mp_rcc_base(); 1086 1087 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1088 } 1089 1090 /* Oscillators and PLLs are not gated at runtime */ 1091 static bool clock_is_always_on(unsigned long id) 1092 { 1093 switch (id) { 1094 case CK_HSE: 1095 case CK_CSI: 1096 case CK_LSI: 1097 case CK_LSE: 1098 case CK_HSI: 1099 case CK_HSE_DIV2: 1100 case PLL1_Q: 1101 case PLL1_R: 1102 case PLL2_P: 1103 case PLL2_Q: 1104 case PLL2_R: 1105 case PLL3_P: 1106 case PLL3_Q: 1107 case PLL3_R: 1108 case CK_AXI: 1109 case CK_MPU: 1110 case CK_MCU: 1111 case RTC: 1112 return true; 1113 default: 1114 return false; 1115 } 1116 } 1117 1118 static void __stm32mp1_clk_enable(unsigned long id, bool with_refcnt) 1119 { 1120 const struct stm32mp1_clk_gate *gate; 1121 int i; 1122 1123 if (clock_is_always_on(id)) { 1124 return; 1125 } 1126 1127 i = stm32mp1_clk_get_gated_id(id); 1128 if (i < 0) { 1129 ERROR("Clock %lu can't be enabled\n", id); 1130 panic(); 1131 } 1132 1133 gate = gate_ref(i); 1134 1135 if (!with_refcnt) { 1136 __clk_enable(gate); 1137 return; 1138 } 1139 1140 #if defined(IMAGE_BL32) 1141 if (gate_is_non_secure(gate)) { 1142 /* Enable non-secure clock w/o any refcounting */ 1143 __clk_enable(gate); 1144 return; 1145 } 1146 #endif 1147 1148 stm32mp1_clk_lock(&refcount_lock); 1149 1150 if (gate_refcounts[i] == 0U) { 1151 __clk_enable(gate); 1152 } 1153 1154 gate_refcounts[i]++; 1155 if (gate_refcounts[i] == UINT_MAX) { 1156 ERROR("Clock %lu refcount reached max value\n", id); 1157 panic(); 1158 } 1159 1160 stm32mp1_clk_unlock(&refcount_lock); 1161 } 1162 1163 static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt) 1164 { 1165 const struct stm32mp1_clk_gate *gate; 1166 int i; 1167 1168 if (clock_is_always_on(id)) { 1169 return; 1170 } 1171 1172 i = stm32mp1_clk_get_gated_id(id); 1173 if (i < 0) { 1174 ERROR("Clock %lu can't be disabled\n", id); 1175 panic(); 1176 } 1177 1178 gate = gate_ref(i); 1179 1180 if (!with_refcnt) { 1181 __clk_disable(gate); 1182 return; 1183 } 1184 1185 #if defined(IMAGE_BL32) 1186 if (gate_is_non_secure(gate)) { 1187 /* Don't disable non-secure clocks */ 1188 return; 1189 } 1190 #endif 1191 1192 stm32mp1_clk_lock(&refcount_lock); 1193 1194 if (gate_refcounts[i] == 0U) { 1195 ERROR("Clock %lu refcount reached 0\n", id); 1196 panic(); 1197 } 1198 gate_refcounts[i]--; 1199 1200 if (gate_refcounts[i] == 0U) { 1201 __clk_disable(gate); 1202 } 1203 1204 stm32mp1_clk_unlock(&refcount_lock); 1205 } 1206 1207 static int stm32mp_clk_enable(unsigned long id) 1208 { 1209 __stm32mp1_clk_enable(id, true); 1210 1211 return 0; 1212 } 1213 1214 static void stm32mp_clk_disable(unsigned long id) 1215 { 1216 __stm32mp1_clk_disable(id, true); 1217 } 1218 1219 static bool stm32mp_clk_is_enabled(unsigned long id) 1220 { 1221 int i; 1222 1223 if (clock_is_always_on(id)) { 1224 return true; 1225 } 1226 1227 i = stm32mp1_clk_get_gated_id(id); 1228 if (i < 0) { 1229 panic(); 1230 } 1231 1232 return __clk_is_enabled(gate_ref(i)); 1233 } 1234 1235 static unsigned long stm32mp_clk_get_rate(unsigned long id) 1236 { 1237 uintptr_t rcc_base = stm32mp_rcc_base(); 1238 int p = stm32mp1_clk_get_parent(id); 1239 uint32_t prescaler, timpre; 1240 unsigned long parent_rate; 1241 1242 if (p < 0) { 1243 return 0; 1244 } 1245 1246 parent_rate = get_clock_rate(p); 1247 1248 switch (id) { 1249 case TIM2_K: 1250 case TIM3_K: 1251 case TIM4_K: 1252 case TIM5_K: 1253 case TIM6_K: 1254 case TIM7_K: 1255 case TIM12_K: 1256 case TIM13_K: 1257 case TIM14_K: 1258 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) & 1259 RCC_APBXDIV_MASK; 1260 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) & 1261 RCC_TIMGXPRER_TIMGXPRE; 1262 break; 1263 1264 case TIM1_K: 1265 case TIM8_K: 1266 case TIM15_K: 1267 case TIM16_K: 1268 case TIM17_K: 1269 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) & 1270 RCC_APBXDIV_MASK; 1271 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) & 1272 RCC_TIMGXPRER_TIMGXPRE; 1273 break; 1274 1275 default: 1276 return parent_rate; 1277 } 1278 1279 if (prescaler == 0U) { 1280 return parent_rate; 1281 } 1282 1283 return parent_rate * (timpre + 1U) * 2U; 1284 } 1285 1286 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1287 { 1288 uintptr_t address = stm32mp_rcc_base() + offset; 1289 1290 if (enable) { 1291 mmio_setbits_32(address, mask_on); 1292 } else { 1293 mmio_clrbits_32(address, mask_on); 1294 } 1295 } 1296 1297 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1298 { 1299 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1300 uintptr_t address = stm32mp_rcc_base() + offset; 1301 1302 mmio_write_32(address, mask_on); 1303 } 1304 1305 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1306 { 1307 uint64_t timeout; 1308 uint32_t mask_test; 1309 uintptr_t address = stm32mp_rcc_base() + offset; 1310 1311 if (enable) { 1312 mask_test = mask_rdy; 1313 } else { 1314 mask_test = 0; 1315 } 1316 1317 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1318 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1319 if (timeout_elapsed(timeout)) { 1320 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1321 mask_rdy, address, enable, mmio_read_32(address)); 1322 return -ETIMEDOUT; 1323 } 1324 } 1325 1326 return 0; 1327 } 1328 1329 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1330 { 1331 uint32_t value; 1332 uintptr_t rcc_base = stm32mp_rcc_base(); 1333 1334 if (digbyp) { 1335 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1336 } 1337 1338 if (bypass || digbyp) { 1339 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1340 } 1341 1342 /* 1343 * Warning: not recommended to switch directly from "high drive" 1344 * to "medium low drive", and vice-versa. 1345 */ 1346 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1347 RCC_BDCR_LSEDRV_SHIFT; 1348 1349 while (value != lsedrv) { 1350 if (value > lsedrv) { 1351 value--; 1352 } else { 1353 value++; 1354 } 1355 1356 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1357 RCC_BDCR_LSEDRV_MASK, 1358 value << RCC_BDCR_LSEDRV_SHIFT); 1359 } 1360 1361 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1362 } 1363 1364 static void stm32mp1_lse_wait(void) 1365 { 1366 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1367 VERBOSE("%s: failed\n", __func__); 1368 } 1369 } 1370 1371 static void stm32mp1_lsi_set(bool enable) 1372 { 1373 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1374 1375 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1376 VERBOSE("%s: failed\n", __func__); 1377 } 1378 } 1379 1380 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1381 { 1382 uintptr_t rcc_base = stm32mp_rcc_base(); 1383 1384 if (digbyp) { 1385 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1386 } 1387 1388 if (bypass || digbyp) { 1389 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1390 } 1391 1392 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1393 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1394 VERBOSE("%s: failed\n", __func__); 1395 } 1396 1397 if (css) { 1398 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1399 } 1400 1401 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 1402 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) && 1403 (!(digbyp || bypass))) { 1404 panic(); 1405 } 1406 #endif 1407 } 1408 1409 static void stm32mp1_csi_set(bool enable) 1410 { 1411 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1412 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1413 VERBOSE("%s: failed\n", __func__); 1414 } 1415 } 1416 1417 static void stm32mp1_hsi_set(bool enable) 1418 { 1419 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1420 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1421 VERBOSE("%s: failed\n", __func__); 1422 } 1423 } 1424 1425 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1426 { 1427 uint64_t timeout; 1428 uintptr_t rcc_base = stm32mp_rcc_base(); 1429 uintptr_t address = rcc_base + RCC_OCRDYR; 1430 1431 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1432 RCC_HSICFGR_HSIDIV_MASK, 1433 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1434 1435 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1436 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1437 if (timeout_elapsed(timeout)) { 1438 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1439 address, mmio_read_32(address)); 1440 return -ETIMEDOUT; 1441 } 1442 } 1443 1444 return 0; 1445 } 1446 1447 static int stm32mp1_hsidiv(unsigned long hsifreq) 1448 { 1449 uint8_t hsidiv; 1450 uint32_t hsidivfreq = MAX_HSI_HZ; 1451 1452 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1453 if (hsidivfreq == hsifreq) { 1454 break; 1455 } 1456 1457 hsidivfreq /= 2U; 1458 } 1459 1460 if (hsidiv == 4U) { 1461 ERROR("Invalid clk-hsi frequency\n"); 1462 return -1; 1463 } 1464 1465 if (hsidiv != 0U) { 1466 return stm32mp1_set_hsidiv(hsidiv); 1467 } 1468 1469 return 0; 1470 } 1471 1472 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1473 unsigned int clksrc, 1474 uint32_t *pllcfg, int plloff) 1475 { 1476 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1477 uintptr_t rcc_base = stm32mp_rcc_base(); 1478 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1479 enum stm32mp1_plltype type = pll->plltype; 1480 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1481 unsigned long refclk; 1482 uint32_t ifrge = 0U; 1483 uint32_t src, value, fracv = 0; 1484 void *fdt; 1485 1486 /* Check PLL output */ 1487 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1488 return false; 1489 } 1490 1491 /* Check current clksrc */ 1492 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1493 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1494 return false; 1495 } 1496 1497 /* Check Div */ 1498 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1499 1500 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1501 (pllcfg[PLLCFG_M] + 1U); 1502 1503 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1504 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1505 return false; 1506 } 1507 1508 if ((type == PLL_800) && (refclk >= 8000000U)) { 1509 ifrge = 1U; 1510 } 1511 1512 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1513 RCC_PLLNCFGR1_DIVN_MASK; 1514 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1515 RCC_PLLNCFGR1_DIVM_MASK; 1516 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1517 RCC_PLLNCFGR1_IFRGE_MASK; 1518 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1519 return false; 1520 } 1521 1522 /* Fractional configuration */ 1523 if (fdt_get_address(&fdt) == 1) { 1524 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1525 } 1526 1527 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1528 value |= RCC_PLLNFRACR_FRACLE; 1529 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1530 return false; 1531 } 1532 1533 /* Output config */ 1534 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1535 RCC_PLLNCFGR2_DIVP_MASK; 1536 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1537 RCC_PLLNCFGR2_DIVQ_MASK; 1538 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1539 RCC_PLLNCFGR2_DIVR_MASK; 1540 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1541 return false; 1542 } 1543 1544 return true; 1545 } 1546 1547 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1548 { 1549 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1550 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1551 1552 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1553 mmio_clrsetbits_32(pllxcr, 1554 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1555 RCC_PLLNCR_DIVREN, 1556 RCC_PLLNCR_PLLON); 1557 } 1558 1559 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1560 { 1561 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1562 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1563 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1564 1565 /* Wait PLL lock */ 1566 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1567 if (timeout_elapsed(timeout)) { 1568 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1569 pll_id, pllxcr, mmio_read_32(pllxcr)); 1570 return -ETIMEDOUT; 1571 } 1572 } 1573 1574 /* Start the requested output */ 1575 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1576 1577 return 0; 1578 } 1579 1580 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1581 { 1582 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1583 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1584 uint64_t timeout; 1585 1586 /* Stop all output */ 1587 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1588 RCC_PLLNCR_DIVREN); 1589 1590 /* Stop PLL */ 1591 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1592 1593 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1594 /* Wait PLL stopped */ 1595 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1596 if (timeout_elapsed(timeout)) { 1597 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1598 pll_id, pllxcr, mmio_read_32(pllxcr)); 1599 return -ETIMEDOUT; 1600 } 1601 } 1602 1603 return 0; 1604 } 1605 1606 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1607 uint32_t *pllcfg) 1608 { 1609 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1610 uintptr_t rcc_base = stm32mp_rcc_base(); 1611 uint32_t value; 1612 1613 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1614 RCC_PLLNCFGR2_DIVP_MASK; 1615 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1616 RCC_PLLNCFGR2_DIVQ_MASK; 1617 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1618 RCC_PLLNCFGR2_DIVR_MASK; 1619 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1620 } 1621 1622 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1623 uint32_t *pllcfg, uint32_t fracv) 1624 { 1625 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1626 uintptr_t rcc_base = stm32mp_rcc_base(); 1627 enum stm32mp1_plltype type = pll->plltype; 1628 unsigned long refclk; 1629 uint32_t ifrge = 0; 1630 uint32_t src, value; 1631 1632 src = mmio_read_32(rcc_base + pll->rckxselr) & 1633 RCC_SELR_REFCLK_SRC_MASK; 1634 1635 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1636 (pllcfg[PLLCFG_M] + 1U); 1637 1638 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1639 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1640 return -EINVAL; 1641 } 1642 1643 if ((type == PLL_800) && (refclk >= 8000000U)) { 1644 ifrge = 1U; 1645 } 1646 1647 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1648 RCC_PLLNCFGR1_DIVN_MASK; 1649 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1650 RCC_PLLNCFGR1_DIVM_MASK; 1651 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1652 RCC_PLLNCFGR1_IFRGE_MASK; 1653 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1654 1655 /* Fractional configuration */ 1656 value = 0; 1657 mmio_write_32(rcc_base + pll->pllxfracr, value); 1658 1659 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1660 mmio_write_32(rcc_base + pll->pllxfracr, value); 1661 1662 value |= RCC_PLLNFRACR_FRACLE; 1663 mmio_write_32(rcc_base + pll->pllxfracr, value); 1664 1665 stm32mp1_pll_config_output(pll_id, pllcfg); 1666 1667 return 0; 1668 } 1669 1670 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1671 { 1672 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1673 uint32_t pllxcsg = 0; 1674 1675 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1676 RCC_PLLNCSGR_MOD_PER_MASK; 1677 1678 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1679 RCC_PLLNCSGR_INC_STEP_MASK; 1680 1681 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1682 RCC_PLLNCSGR_SSCG_MODE_MASK; 1683 1684 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1685 1686 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1687 RCC_PLLNCR_SSCG_CTRL); 1688 } 1689 1690 static int stm32mp1_set_clksrc(unsigned int clksrc) 1691 { 1692 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1693 uint64_t timeout; 1694 1695 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1696 clksrc & RCC_SELR_SRC_MASK); 1697 1698 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1699 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1700 if (timeout_elapsed(timeout)) { 1701 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1702 clksrc_address, mmio_read_32(clksrc_address)); 1703 return -ETIMEDOUT; 1704 } 1705 } 1706 1707 return 0; 1708 } 1709 1710 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1711 { 1712 uint64_t timeout; 1713 1714 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1715 clkdiv & RCC_DIVR_DIV_MASK); 1716 1717 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1718 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1719 if (timeout_elapsed(timeout)) { 1720 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1721 clkdiv, address, mmio_read_32(address)); 1722 return -ETIMEDOUT; 1723 } 1724 } 1725 1726 return 0; 1727 } 1728 1729 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1730 { 1731 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1732 1733 /* 1734 * Binding clksrc : 1735 * bit15-4 offset 1736 * bit3: disable 1737 * bit2-0: MCOSEL[2:0] 1738 */ 1739 if ((clksrc & 0x8U) != 0U) { 1740 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1741 } else { 1742 mmio_clrsetbits_32(clksrc_address, 1743 RCC_MCOCFG_MCOSRC_MASK, 1744 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1745 mmio_clrsetbits_32(clksrc_address, 1746 RCC_MCOCFG_MCODIV_MASK, 1747 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1748 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1749 } 1750 } 1751 1752 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1753 { 1754 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1755 1756 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1757 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1758 mmio_clrsetbits_32(address, 1759 RCC_BDCR_RTCSRC_MASK, 1760 (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); 1761 1762 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1763 } 1764 1765 if (lse_css) { 1766 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1767 } 1768 } 1769 1770 static void stm32mp1_stgen_config(void) 1771 { 1772 uint32_t cntfid0; 1773 unsigned long rate; 1774 unsigned long long counter; 1775 1776 cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF); 1777 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1778 1779 if (cntfid0 == rate) { 1780 return; 1781 } 1782 1783 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1784 counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1785 counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32; 1786 counter = (counter * rate / cntfid0); 1787 1788 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); 1789 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1790 mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); 1791 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1792 1793 write_cntfrq((u_register_t)rate); 1794 1795 /* Need to update timer with new frequency */ 1796 generic_delay_timer_init(); 1797 } 1798 1799 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1800 { 1801 unsigned long long cnt; 1802 1803 cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) | 1804 mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1805 1806 cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U; 1807 1808 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1809 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt); 1810 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1811 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1812 } 1813 1814 static void stm32mp1_pkcs_config(uint32_t pkcs) 1815 { 1816 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1817 uint32_t value = pkcs & 0xFU; 1818 uint32_t mask = 0xFU; 1819 1820 if ((pkcs & BIT(31)) != 0U) { 1821 mask <<= 4; 1822 value <<= 4; 1823 } 1824 1825 mmio_clrsetbits_32(address, mask, value); 1826 } 1827 1828 static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg, 1829 uint32_t *fracv, uint32_t *csg, 1830 bool *csg_set) 1831 { 1832 void *fdt; 1833 int ret; 1834 1835 if (fdt_get_address(&fdt) == 0) { 1836 return -FDT_ERR_NOTFOUND; 1837 } 1838 1839 ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB, 1840 pllcfg); 1841 if (ret < 0) { 1842 return -FDT_ERR_NOTFOUND; 1843 } 1844 1845 *fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1846 1847 ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB, 1848 csg); 1849 1850 *csg_set = (ret == 0); 1851 1852 if (ret == -FDT_ERR_NOTFOUND) { 1853 ret = 0; 1854 } 1855 1856 return ret; 1857 } 1858 1859 int stm32mp1_clk_init(void) 1860 { 1861 uintptr_t rcc_base = stm32mp_rcc_base(); 1862 uint32_t pllfracv[_PLL_NB]; 1863 uint32_t pllcsg[_PLL_NB][PLLCSG_NB]; 1864 unsigned int clksrc[CLKSRC_NB]; 1865 unsigned int clkdiv[CLKDIV_NB]; 1866 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1867 int plloff[_PLL_NB]; 1868 int ret, len; 1869 enum stm32mp1_pll_id i; 1870 bool pllcsg_set[_PLL_NB]; 1871 bool pllcfg_valid[_PLL_NB]; 1872 bool lse_css = false; 1873 bool pll3_preserve = false; 1874 bool pll4_preserve = false; 1875 bool pll4_bootrom = false; 1876 const fdt32_t *pkcs_cell; 1877 void *fdt; 1878 int stgen_p = stm32mp1_clk_get_parent(STGEN_K); 1879 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K); 1880 1881 if (fdt_get_address(&fdt) == 0) { 1882 return -FDT_ERR_NOTFOUND; 1883 } 1884 1885 /* Check status field to disable security */ 1886 if (!fdt_get_rcc_secure_status()) { 1887 mmio_write_32(rcc_base + RCC_TZCR, 0); 1888 } 1889 1890 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1891 clksrc); 1892 if (ret < 0) { 1893 return -FDT_ERR_NOTFOUND; 1894 } 1895 1896 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1897 clkdiv); 1898 if (ret < 0) { 1899 return -FDT_ERR_NOTFOUND; 1900 } 1901 1902 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1903 char name[12]; 1904 1905 snprintf(name, sizeof(name), "st,pll@%d", i); 1906 plloff[i] = fdt_rcc_subnode_offset(name); 1907 1908 pllcfg_valid[i] = fdt_check_node(plloff[i]); 1909 if (!pllcfg_valid[i]) { 1910 continue; 1911 } 1912 1913 ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i], 1914 &pllfracv[i], pllcsg[i], 1915 &pllcsg_set[i]); 1916 if (ret != 0) { 1917 return ret; 1918 } 1919 } 1920 1921 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1922 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1923 1924 /* 1925 * Switch ON oscillator found in device-tree. 1926 * Note: HSI already ON after BootROM stage. 1927 */ 1928 if (stm32mp1_osc[_LSI] != 0U) { 1929 stm32mp1_lsi_set(true); 1930 } 1931 if (stm32mp1_osc[_LSE] != 0U) { 1932 const char *name = stm32mp_osc_node_label[_LSE]; 1933 bool bypass, digbyp; 1934 uint32_t lsedrv; 1935 1936 bypass = fdt_clk_read_bool(name, "st,bypass"); 1937 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 1938 lse_css = fdt_clk_read_bool(name, "st,css"); 1939 lsedrv = fdt_clk_read_uint32_default(name, "st,drive", 1940 LSEDRV_MEDIUM_HIGH); 1941 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1942 } 1943 if (stm32mp1_osc[_HSE] != 0U) { 1944 const char *name = stm32mp_osc_node_label[_HSE]; 1945 bool bypass, digbyp, css; 1946 1947 bypass = fdt_clk_read_bool(name, "st,bypass"); 1948 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 1949 css = fdt_clk_read_bool(name, "st,css"); 1950 stm32mp1_hse_enable(bypass, digbyp, css); 1951 } 1952 /* 1953 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1954 * => switch on CSI even if node is not present in device tree 1955 */ 1956 stm32mp1_csi_set(true); 1957 1958 /* Come back to HSI */ 1959 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1960 if (ret != 0) { 1961 return ret; 1962 } 1963 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1964 if (ret != 0) { 1965 return ret; 1966 } 1967 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1968 if (ret != 0) { 1969 return ret; 1970 } 1971 1972 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1973 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1974 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1975 clksrc[CLKSRC_PLL3], 1976 pllcfg[_PLL3], 1977 plloff[_PLL3]); 1978 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1979 clksrc[CLKSRC_PLL4], 1980 pllcfg[_PLL4], 1981 plloff[_PLL4]); 1982 } 1983 /* Don't initialize PLL4, when used by BOOTROM */ 1984 if ((stm32mp_get_boot_itf_selected() == 1985 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && 1986 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) { 1987 pll4_bootrom = true; 1988 pll4_preserve = true; 1989 } 1990 1991 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1992 if (((i == _PLL3) && pll3_preserve) || 1993 ((i == _PLL4) && pll4_preserve)) { 1994 continue; 1995 } 1996 1997 ret = stm32mp1_pll_stop(i); 1998 if (ret != 0) { 1999 return ret; 2000 } 2001 } 2002 2003 /* Configure HSIDIV */ 2004 if (stm32mp1_osc[_HSI] != 0U) { 2005 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 2006 if (ret != 0) { 2007 return ret; 2008 } 2009 stm32mp1_stgen_config(); 2010 } 2011 2012 /* Select DIV */ 2013 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 2014 mmio_write_32(rcc_base + RCC_MPCKDIVR, 2015 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 2016 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 2017 if (ret != 0) { 2018 return ret; 2019 } 2020 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 2021 if (ret != 0) { 2022 return ret; 2023 } 2024 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 2025 if (ret != 0) { 2026 return ret; 2027 } 2028 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 2029 if (ret != 0) { 2030 return ret; 2031 } 2032 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 2033 if (ret != 0) { 2034 return ret; 2035 } 2036 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 2037 if (ret != 0) { 2038 return ret; 2039 } 2040 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 2041 if (ret != 0) { 2042 return ret; 2043 } 2044 2045 /* No ready bit for RTC */ 2046 mmio_write_32(rcc_base + RCC_RTCDIVR, 2047 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 2048 2049 /* Configure PLLs source */ 2050 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 2051 if (ret != 0) { 2052 return ret; 2053 } 2054 2055 if (!pll3_preserve) { 2056 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 2057 if (ret != 0) { 2058 return ret; 2059 } 2060 } 2061 2062 if (!pll4_preserve) { 2063 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 2064 if (ret != 0) { 2065 return ret; 2066 } 2067 } 2068 2069 /* Configure and start PLLs */ 2070 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2071 if (((i == _PLL3) && pll3_preserve) || 2072 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 2073 continue; 2074 } 2075 2076 if (!pllcfg_valid[i]) { 2077 continue; 2078 } 2079 2080 if ((i == _PLL4) && pll4_bootrom) { 2081 /* Set output divider if not done by the Bootrom */ 2082 stm32mp1_pll_config_output(i, pllcfg[i]); 2083 continue; 2084 } 2085 2086 ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]); 2087 if (ret != 0) { 2088 return ret; 2089 } 2090 2091 if (pllcsg_set[i]) { 2092 stm32mp1_pll_csg(i, pllcsg[i]); 2093 } 2094 2095 stm32mp1_pll_start(i); 2096 } 2097 /* Wait and start PLLs ouptut when ready */ 2098 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2099 if (!pllcfg_valid[i]) { 2100 continue; 2101 } 2102 2103 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 2104 if (ret != 0) { 2105 return ret; 2106 } 2107 } 2108 /* Wait LSE ready before to use it */ 2109 if (stm32mp1_osc[_LSE] != 0U) { 2110 stm32mp1_lse_wait(); 2111 } 2112 2113 /* Configure with expected clock source */ 2114 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 2115 if (ret != 0) { 2116 return ret; 2117 } 2118 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 2119 if (ret != 0) { 2120 return ret; 2121 } 2122 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 2123 if (ret != 0) { 2124 return ret; 2125 } 2126 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 2127 2128 /* Configure PKCK */ 2129 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 2130 if (pkcs_cell != NULL) { 2131 bool ckper_disabled = false; 2132 uint32_t j; 2133 uint32_t usbreg_bootrom = 0U; 2134 2135 if (pll4_bootrom) { 2136 usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR); 2137 } 2138 2139 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 2140 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 2141 2142 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 2143 ckper_disabled = true; 2144 continue; 2145 } 2146 stm32mp1_pkcs_config(pkcs); 2147 } 2148 2149 /* 2150 * CKPER is source for some peripheral clocks 2151 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2152 * only if previous clock is still ON 2153 * => deactivated CKPER only after switching clock 2154 */ 2155 if (ckper_disabled) { 2156 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 2157 } 2158 2159 if (pll4_bootrom) { 2160 uint32_t usbreg_value, usbreg_mask; 2161 const struct stm32mp1_clk_sel *sel; 2162 2163 sel = clk_sel_ref(_USBPHY_SEL); 2164 usbreg_mask = (uint32_t)sel->msk << sel->src; 2165 sel = clk_sel_ref(_USBO_SEL); 2166 usbreg_mask |= (uint32_t)sel->msk << sel->src; 2167 2168 usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) & 2169 usbreg_mask; 2170 usbreg_bootrom &= usbreg_mask; 2171 if (usbreg_bootrom != usbreg_value) { 2172 VERBOSE("forbidden new USB clk path\n"); 2173 VERBOSE("vs bootrom on USB boot\n"); 2174 return -FDT_ERR_BADVALUE; 2175 } 2176 } 2177 } 2178 2179 /* Switch OFF HSI if not found in device-tree */ 2180 if (stm32mp1_osc[_HSI] == 0U) { 2181 stm32mp1_hsi_set(false); 2182 } 2183 stm32mp1_stgen_config(); 2184 2185 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2186 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 2187 RCC_DDRITFCR_DDRCKMOD_MASK, 2188 RCC_DDRITFCR_DDRCKMOD_SSR << 2189 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2190 2191 return 0; 2192 } 2193 2194 static void stm32mp1_osc_clk_init(const char *name, 2195 enum stm32mp_osc_id index) 2196 { 2197 uint32_t frequency; 2198 2199 if (fdt_osc_read_freq(name, &frequency) == 0) { 2200 stm32mp1_osc[index] = frequency; 2201 } 2202 } 2203 2204 static void stm32mp1_osc_init(void) 2205 { 2206 enum stm32mp_osc_id i; 2207 2208 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2209 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2210 } 2211 } 2212 2213 #ifdef STM32MP_SHARED_RESOURCES 2214 /* 2215 * Get the parent ID of the target parent clock, for tagging as secure 2216 * shared clock dependencies. 2217 */ 2218 static int get_parent_id_parent(unsigned int parent_id) 2219 { 2220 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2221 enum stm32mp1_pll_id pll_id; 2222 uint32_t p_sel; 2223 uintptr_t rcc_base = stm32mp_rcc_base(); 2224 2225 switch (parent_id) { 2226 case _ACLK: 2227 case _PCLK4: 2228 case _PCLK5: 2229 s = _AXIS_SEL; 2230 break; 2231 case _PLL1_P: 2232 case _PLL1_Q: 2233 case _PLL1_R: 2234 pll_id = _PLL1; 2235 break; 2236 case _PLL2_P: 2237 case _PLL2_Q: 2238 case _PLL2_R: 2239 pll_id = _PLL2; 2240 break; 2241 case _PLL3_P: 2242 case _PLL3_Q: 2243 case _PLL3_R: 2244 pll_id = _PLL3; 2245 break; 2246 case _PLL4_P: 2247 case _PLL4_Q: 2248 case _PLL4_R: 2249 pll_id = _PLL4; 2250 break; 2251 case _PCLK1: 2252 case _PCLK2: 2253 case _HCLK2: 2254 case _HCLK6: 2255 case _CK_PER: 2256 case _CK_MPU: 2257 case _CK_MCU: 2258 case _USB_PHY_48: 2259 /* We do not expect to access these */ 2260 panic(); 2261 break; 2262 default: 2263 /* Other parents have no parent */ 2264 return -1; 2265 } 2266 2267 if (s != _UNKNOWN_SEL) { 2268 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2269 2270 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2271 sel->msk; 2272 2273 if (p_sel < sel->nb_parent) { 2274 return (int)sel->parent[p_sel]; 2275 } 2276 } else { 2277 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2278 2279 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2280 RCC_SELR_REFCLK_SRC_MASK; 2281 2282 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2283 return (int)pll->refclk[p_sel]; 2284 } 2285 } 2286 2287 VERBOSE("No parent selected for %s\n", 2288 stm32mp1_clk_parent_name[parent_id]); 2289 2290 return -1; 2291 } 2292 2293 static void secure_parent_clocks(unsigned long parent_id) 2294 { 2295 int grandparent_id; 2296 2297 switch (parent_id) { 2298 case _PLL3_P: 2299 case _PLL3_Q: 2300 case _PLL3_R: 2301 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2302 break; 2303 2304 /* These clocks are always secure when RCC is secure */ 2305 case _ACLK: 2306 case _HCLK2: 2307 case _HCLK6: 2308 case _PCLK4: 2309 case _PCLK5: 2310 case _PLL1_P: 2311 case _PLL1_Q: 2312 case _PLL1_R: 2313 case _PLL2_P: 2314 case _PLL2_Q: 2315 case _PLL2_R: 2316 case _HSI: 2317 case _HSI_KER: 2318 case _LSI: 2319 case _CSI: 2320 case _CSI_KER: 2321 case _HSE: 2322 case _HSE_KER: 2323 case _HSE_KER_DIV2: 2324 case _HSE_RTC: 2325 case _LSE: 2326 break; 2327 2328 default: 2329 VERBOSE("Cannot secure parent clock %s\n", 2330 stm32mp1_clk_parent_name[parent_id]); 2331 panic(); 2332 } 2333 2334 grandparent_id = get_parent_id_parent(parent_id); 2335 if (grandparent_id >= 0) { 2336 secure_parent_clocks(grandparent_id); 2337 } 2338 } 2339 2340 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2341 { 2342 int parent_id; 2343 2344 if (!stm32mp1_rcc_is_secure()) { 2345 return; 2346 } 2347 2348 switch (clock_id) { 2349 case PLL1: 2350 case PLL2: 2351 /* PLL1/PLL2 are always secure: nothing to do */ 2352 break; 2353 case PLL3: 2354 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2355 break; 2356 case PLL4: 2357 ERROR("PLL4 cannot be secured\n"); 2358 panic(); 2359 break; 2360 default: 2361 /* Others are expected gateable clock */ 2362 parent_id = stm32mp1_clk_get_parent(clock_id); 2363 if (parent_id < 0) { 2364 INFO("No parent found for clock %lu\n", clock_id); 2365 } else { 2366 secure_parent_clocks(parent_id); 2367 } 2368 break; 2369 } 2370 } 2371 #endif /* STM32MP_SHARED_RESOURCES */ 2372 2373 static void sync_earlyboot_clocks_state(void) 2374 { 2375 unsigned int idx; 2376 const unsigned long secure_enable[] = { 2377 AXIDCG, 2378 BSEC, 2379 DDRC1, DDRC1LP, 2380 DDRC2, DDRC2LP, 2381 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2382 DDRPHYC, DDRPHYCLP, 2383 RTCAPB, 2384 TZC1, TZC2, 2385 TZPC, 2386 STGEN_K, 2387 }; 2388 2389 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2390 stm32mp_clk_enable(secure_enable[idx]); 2391 } 2392 } 2393 2394 static const struct clk_ops stm32mp_clk_ops = { 2395 .enable = stm32mp_clk_enable, 2396 .disable = stm32mp_clk_disable, 2397 .is_enabled = stm32mp_clk_is_enabled, 2398 .get_rate = stm32mp_clk_get_rate, 2399 .get_parent = stm32mp1_clk_get_parent, 2400 }; 2401 2402 int stm32mp1_clk_probe(void) 2403 { 2404 stm32mp1_osc_init(); 2405 2406 sync_earlyboot_clocks_state(); 2407 2408 clk_register(&stm32mp_clk_ops); 2409 2410 return 0; 2411 } 2412