1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp1_dbgmcu.h> 26 #include <stm32mp1_private.h> 27 #include <stm32mp1_shared_resources.h> 28 #endif 29 30 #if !STM32MP_USE_STM32IMAGE 31 #include "stm32mp1_fip_def.h" 32 #else /* STM32MP_USE_STM32IMAGE */ 33 #include "stm32mp1_stm32image_def.h" 34 #endif /* STM32MP_USE_STM32IMAGE */ 35 36 /******************************************************************************* 37 * CHIP ID 38 ******************************************************************************/ 39 #define STM32MP1_CHIP_ID U(0x500) 40 41 #define STM32MP157C_PART_NB U(0x05000000) 42 #define STM32MP157A_PART_NB U(0x05000001) 43 #define STM32MP153C_PART_NB U(0x05000024) 44 #define STM32MP153A_PART_NB U(0x05000025) 45 #define STM32MP151C_PART_NB U(0x0500002E) 46 #define STM32MP151A_PART_NB U(0x0500002F) 47 #define STM32MP157F_PART_NB U(0x05000080) 48 #define STM32MP157D_PART_NB U(0x05000081) 49 #define STM32MP153F_PART_NB U(0x050000A4) 50 #define STM32MP153D_PART_NB U(0x050000A5) 51 #define STM32MP151F_PART_NB U(0x050000AE) 52 #define STM32MP151D_PART_NB U(0x050000AF) 53 54 #define STM32MP1_REV_B U(0x2000) 55 #define STM32MP1_REV_Z U(0x2001) 56 57 /******************************************************************************* 58 * PACKAGE ID 59 ******************************************************************************/ 60 #define PKG_AA_LFBGA448 U(4) 61 #define PKG_AB_LFBGA354 U(3) 62 #define PKG_AC_TFBGA361 U(2) 63 #define PKG_AD_TFBGA257 U(1) 64 65 /******************************************************************************* 66 * STM32MP1 memory map related constants 67 ******************************************************************************/ 68 #define STM32MP_ROM_BASE U(0x00000000) 69 #define STM32MP_ROM_SIZE U(0x00020000) 70 #define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000) 71 72 #if STM32MP13 73 #define STM32MP_SYSRAM_BASE U(0x2FFE0000) 74 #define STM32MP_SYSRAM_SIZE U(0x00020000) 75 #define SRAM1_BASE U(0x30000000) 76 #define SRAM1_SIZE U(0x00004000) 77 #define SRAM2_BASE U(0x30004000) 78 #define SRAM2_SIZE U(0x00002000) 79 #define SRAM3_BASE U(0x30006000) 80 #define SRAM3_SIZE U(0x00002000) 81 #endif /* STM32MP13 */ 82 #if STM32MP15 83 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 84 #define STM32MP_SYSRAM_SIZE U(0x00040000) 85 #endif /* STM32MP15 */ 86 87 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE 88 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ 89 STM32MP_SYSRAM_SIZE - \ 90 STM32MP_NS_SYSRAM_SIZE) 91 92 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE 93 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE 94 95 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 96 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ 97 STM32MP_NS_SYSRAM_SIZE) 98 99 /* DDR configuration */ 100 #define STM32MP_DDR_BASE U(0xC0000000) 101 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 102 103 /* DDR power initializations */ 104 #ifndef __ASSEMBLER__ 105 enum ddr_type { 106 STM32MP_DDR3, 107 STM32MP_LPDDR2, 108 STM32MP_LPDDR3 109 }; 110 #endif 111 112 /* Section used inside TF binaries */ 113 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 114 /* 256 Octets reserved for header */ 115 #define STM32MP_HEADER_SIZE U(0x00000100) 116 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 117 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 118 119 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ 120 STM32MP_PARAM_LOAD_SIZE + \ 121 STM32MP_HEADER_SIZE) 122 123 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 124 (STM32MP_PARAM_LOAD_SIZE + \ 125 STM32MP_HEADER_SIZE)) 126 127 /* BL2 and BL32/sp_min require finer granularity tables */ 128 #if defined(IMAGE_BL2) 129 #define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */ 130 #endif 131 132 #if defined(IMAGE_BL32) 133 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 134 #endif 135 136 /* 137 * MAX_MMAP_REGIONS is usually: 138 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 139 */ 140 #if defined(IMAGE_BL2) 141 #if STM32MP_USB_PROGRAMMER 142 #define MAX_MMAP_REGIONS 8 143 #else 144 #define MAX_MMAP_REGIONS 7 145 #endif 146 #endif 147 148 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 149 #define STM32MP_BL33_MAX_SIZE U(0x400000) 150 151 /* Define maximum page size for NAND devices */ 152 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 153 154 /******************************************************************************* 155 * STM32MP1 device/io map related constants (used for MMU) 156 ******************************************************************************/ 157 #define STM32MP1_DEVICE1_BASE U(0x40000000) 158 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 159 160 #define STM32MP1_DEVICE2_BASE U(0x80000000) 161 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 162 163 /******************************************************************************* 164 * STM32MP1 RCC 165 ******************************************************************************/ 166 #define RCC_BASE U(0x50000000) 167 168 /******************************************************************************* 169 * STM32MP1 PWR 170 ******************************************************************************/ 171 #define PWR_BASE U(0x50001000) 172 173 /******************************************************************************* 174 * STM32MP1 GPIO 175 ******************************************************************************/ 176 #define GPIOA_BASE U(0x50002000) 177 #define GPIOB_BASE U(0x50003000) 178 #define GPIOC_BASE U(0x50004000) 179 #define GPIOD_BASE U(0x50005000) 180 #define GPIOE_BASE U(0x50006000) 181 #define GPIOF_BASE U(0x50007000) 182 #define GPIOG_BASE U(0x50008000) 183 #define GPIOH_BASE U(0x50009000) 184 #define GPIOI_BASE U(0x5000A000) 185 #if STM32MP15 186 #define GPIOJ_BASE U(0x5000B000) 187 #define GPIOK_BASE U(0x5000C000) 188 #define GPIOZ_BASE U(0x54004000) 189 #endif 190 #define GPIO_BANK_OFFSET U(0x1000) 191 192 /* Bank IDs used in GPIO driver API */ 193 #define GPIO_BANK_A U(0) 194 #define GPIO_BANK_B U(1) 195 #define GPIO_BANK_C U(2) 196 #define GPIO_BANK_D U(3) 197 #define GPIO_BANK_E U(4) 198 #define GPIO_BANK_F U(5) 199 #define GPIO_BANK_G U(6) 200 #define GPIO_BANK_H U(7) 201 #define GPIO_BANK_I U(8) 202 #if STM32MP15 203 #define GPIO_BANK_J U(9) 204 #define GPIO_BANK_K U(10) 205 #define GPIO_BANK_Z U(25) 206 207 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 208 #endif 209 210 /******************************************************************************* 211 * STM32MP1 UART 212 ******************************************************************************/ 213 #define USART1_BASE U(0x5C000000) 214 #define USART2_BASE U(0x4000E000) 215 #define USART3_BASE U(0x4000F000) 216 #define UART4_BASE U(0x40010000) 217 #define UART5_BASE U(0x40011000) 218 #define USART6_BASE U(0x44003000) 219 #define UART7_BASE U(0x40018000) 220 #define UART8_BASE U(0x40019000) 221 222 /* For UART crash console */ 223 #define STM32MP_DEBUG_USART_BASE UART4_BASE 224 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 225 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 226 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 227 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 228 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 229 #define DEBUG_UART_TX_GPIO_PORT 11 230 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 231 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 232 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 233 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 234 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 235 #define DEBUG_UART_RST_REG RCC_APB1RSTSETR 236 #define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST 237 238 /******************************************************************************* 239 * STM32MP1 ETZPC 240 ******************************************************************************/ 241 #define STM32MP1_ETZPC_BASE U(0x5C007000) 242 243 /* ETZPC TZMA IDs */ 244 #define STM32MP1_ETZPC_TZMA_ROM U(0) 245 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 246 247 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 248 249 /* ETZPC DECPROT IDs */ 250 #define STM32MP1_ETZPC_STGENC_ID 0 251 #define STM32MP1_ETZPC_BKPSRAM_ID 1 252 #define STM32MP1_ETZPC_IWDG1_ID 2 253 #define STM32MP1_ETZPC_USART1_ID 3 254 #define STM32MP1_ETZPC_SPI6_ID 4 255 #define STM32MP1_ETZPC_I2C4_ID 5 256 #define STM32MP1_ETZPC_RNG1_ID 7 257 #define STM32MP1_ETZPC_HASH1_ID 8 258 #define STM32MP1_ETZPC_CRYP1_ID 9 259 #define STM32MP1_ETZPC_DDRCTRL_ID 10 260 #define STM32MP1_ETZPC_DDRPHYC_ID 11 261 #define STM32MP1_ETZPC_I2C6_ID 12 262 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 263 264 #define STM32MP1_ETZPC_TIM2_ID 16 265 #define STM32MP1_ETZPC_TIM3_ID 17 266 #define STM32MP1_ETZPC_TIM4_ID 18 267 #define STM32MP1_ETZPC_TIM5_ID 19 268 #define STM32MP1_ETZPC_TIM6_ID 20 269 #define STM32MP1_ETZPC_TIM7_ID 21 270 #define STM32MP1_ETZPC_TIM12_ID 22 271 #define STM32MP1_ETZPC_TIM13_ID 23 272 #define STM32MP1_ETZPC_TIM14_ID 24 273 #define STM32MP1_ETZPC_LPTIM1_ID 25 274 #define STM32MP1_ETZPC_WWDG1_ID 26 275 #define STM32MP1_ETZPC_SPI2_ID 27 276 #define STM32MP1_ETZPC_SPI3_ID 28 277 #define STM32MP1_ETZPC_SPDIFRX_ID 29 278 #define STM32MP1_ETZPC_USART2_ID 30 279 #define STM32MP1_ETZPC_USART3_ID 31 280 #define STM32MP1_ETZPC_UART4_ID 32 281 #define STM32MP1_ETZPC_UART5_ID 33 282 #define STM32MP1_ETZPC_I2C1_ID 34 283 #define STM32MP1_ETZPC_I2C2_ID 35 284 #define STM32MP1_ETZPC_I2C3_ID 36 285 #define STM32MP1_ETZPC_I2C5_ID 37 286 #define STM32MP1_ETZPC_CEC_ID 38 287 #define STM32MP1_ETZPC_DAC_ID 39 288 #define STM32MP1_ETZPC_UART7_ID 40 289 #define STM32MP1_ETZPC_UART8_ID 41 290 #define STM32MP1_ETZPC_MDIOS_ID 44 291 #define STM32MP1_ETZPC_TIM1_ID 48 292 #define STM32MP1_ETZPC_TIM8_ID 49 293 #define STM32MP1_ETZPC_USART6_ID 51 294 #define STM32MP1_ETZPC_SPI1_ID 52 295 #define STM32MP1_ETZPC_SPI4_ID 53 296 #define STM32MP1_ETZPC_TIM15_ID 54 297 #define STM32MP1_ETZPC_TIM16_ID 55 298 #define STM32MP1_ETZPC_TIM17_ID 56 299 #define STM32MP1_ETZPC_SPI5_ID 57 300 #define STM32MP1_ETZPC_SAI1_ID 58 301 #define STM32MP1_ETZPC_SAI2_ID 59 302 #define STM32MP1_ETZPC_SAI3_ID 60 303 #define STM32MP1_ETZPC_DFSDM_ID 61 304 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 305 #define STM32MP1_ETZPC_LPTIM2_ID 64 306 #define STM32MP1_ETZPC_LPTIM3_ID 65 307 #define STM32MP1_ETZPC_LPTIM4_ID 66 308 #define STM32MP1_ETZPC_LPTIM5_ID 67 309 #define STM32MP1_ETZPC_SAI4_ID 68 310 #define STM32MP1_ETZPC_VREFBUF_ID 69 311 #define STM32MP1_ETZPC_DCMI_ID 70 312 #define STM32MP1_ETZPC_CRC2_ID 71 313 #define STM32MP1_ETZPC_ADC_ID 72 314 #define STM32MP1_ETZPC_HASH2_ID 73 315 #define STM32MP1_ETZPC_RNG2_ID 74 316 #define STM32MP1_ETZPC_CRYP2_ID 75 317 #define STM32MP1_ETZPC_SRAM1_ID 80 318 #define STM32MP1_ETZPC_SRAM2_ID 81 319 #define STM32MP1_ETZPC_SRAM3_ID 82 320 #define STM32MP1_ETZPC_SRAM4_ID 83 321 #define STM32MP1_ETZPC_RETRAM_ID 84 322 #define STM32MP1_ETZPC_OTG_ID 85 323 #define STM32MP1_ETZPC_SDMMC3_ID 86 324 #define STM32MP1_ETZPC_DLYBSD3_ID 87 325 #define STM32MP1_ETZPC_DMA1_ID 88 326 #define STM32MP1_ETZPC_DMA2_ID 89 327 #define STM32MP1_ETZPC_DMAMUX_ID 90 328 #define STM32MP1_ETZPC_FMC_ID 91 329 #define STM32MP1_ETZPC_QSPI_ID 92 330 #define STM32MP1_ETZPC_DLYBQ_ID 93 331 #define STM32MP1_ETZPC_ETH_ID 94 332 #define STM32MP1_ETZPC_RSV_ID 95 333 334 #define STM32MP_ETZPC_MAX_ID 96 335 336 /******************************************************************************* 337 * STM32MP1 TZC (TZ400) 338 ******************************************************************************/ 339 #define STM32MP1_TZC_BASE U(0x5C006000) 340 341 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \ 342 TZC_400_REGION_ATTR_FILTER_BIT(1)) 343 344 /******************************************************************************* 345 * STM32MP1 SDMMC 346 ******************************************************************************/ 347 #define STM32MP_SDMMC1_BASE U(0x58005000) 348 #define STM32MP_SDMMC2_BASE U(0x58007000) 349 #define STM32MP_SDMMC3_BASE U(0x48004000) 350 351 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 352 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 353 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 354 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 355 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 356 357 /******************************************************************************* 358 * STM32MP1 BSEC / OTP 359 ******************************************************************************/ 360 #define STM32MP1_OTP_MAX_ID 0x5FU 361 #define STM32MP1_UPPER_OTP_START 0x20U 362 363 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 364 365 /* OTP labels */ 366 #define CFG0_OTP "cfg0_otp" 367 #define PART_NUMBER_OTP "part_number_otp" 368 #define PACKAGE_OTP "package_otp" 369 #define HW2_OTP "hw2_otp" 370 #define NAND_OTP "nand_otp" 371 #define MONOTONIC_OTP "monotonic_otp" 372 #define UID_OTP "uid_otp" 373 #define BOARD_ID_OTP "board_id" 374 375 /* OTP mask */ 376 /* CFG0 */ 377 #define CFG0_CLOSED_DEVICE BIT(6) 378 379 /* PART NUMBER */ 380 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 381 #define PART_NUMBER_OTP_PART_SHIFT 0 382 383 /* PACKAGE */ 384 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 385 #define PACKAGE_OTP_PKG_SHIFT 27 386 387 /* IWDG OTP */ 388 #define HW2_OTP_IWDG_HW_POS U(3) 389 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 390 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 391 392 /* HW2 OTP */ 393 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 394 395 /* NAND OTP */ 396 /* NAND parameter storage flag */ 397 #define NAND_PARAM_STORED_IN_OTP BIT(31) 398 399 /* NAND page size in bytes */ 400 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 401 #define NAND_PAGE_SIZE_SHIFT 29 402 #define NAND_PAGE_SIZE_2K U(0) 403 #define NAND_PAGE_SIZE_4K U(1) 404 #define NAND_PAGE_SIZE_8K U(2) 405 406 /* NAND block size in pages */ 407 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 408 #define NAND_BLOCK_SIZE_SHIFT 27 409 #define NAND_BLOCK_SIZE_64_PAGES U(0) 410 #define NAND_BLOCK_SIZE_128_PAGES U(1) 411 #define NAND_BLOCK_SIZE_256_PAGES U(2) 412 413 /* NAND number of block (in unit of 256 blocs) */ 414 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 415 #define NAND_BLOCK_NB_SHIFT 19 416 #define NAND_BLOCK_NB_UNIT U(256) 417 418 /* NAND bus width in bits */ 419 #define NAND_WIDTH_MASK BIT(18) 420 #define NAND_WIDTH_SHIFT 18 421 422 /* NAND number of ECC bits per 512 bytes */ 423 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 424 #define NAND_ECC_BIT_NB_SHIFT 15 425 #define NAND_ECC_BIT_NB_UNSET U(0) 426 #define NAND_ECC_BIT_NB_1_BITS U(1) 427 #define NAND_ECC_BIT_NB_4_BITS U(2) 428 #define NAND_ECC_BIT_NB_8_BITS U(3) 429 #define NAND_ECC_ON_DIE U(4) 430 431 /* NAND number of planes */ 432 #define NAND_PLANE_BIT_NB_MASK BIT(14) 433 434 /* MONOTONIC OTP */ 435 #define MAX_MONOTONIC_VALUE 32 436 437 /* UID OTP */ 438 #define UID_WORD_NB U(3) 439 440 /******************************************************************************* 441 * STM32MP1 TAMP 442 ******************************************************************************/ 443 #define TAMP_BASE U(0x5C00A000) 444 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 445 446 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 447 static inline uintptr_t tamp_bkpr(uint32_t idx) 448 { 449 return TAMP_BKP_REGISTER_BASE + (idx << 2); 450 } 451 #endif 452 453 /******************************************************************************* 454 * STM32MP1 USB 455 ******************************************************************************/ 456 #define USB_OTG_BASE U(0x49000000) 457 458 /******************************************************************************* 459 * STM32MP1 DDRCTRL 460 ******************************************************************************/ 461 #define DDRCTRL_BASE U(0x5A003000) 462 463 /******************************************************************************* 464 * STM32MP1 DDRPHYC 465 ******************************************************************************/ 466 #define DDRPHYC_BASE U(0x5A004000) 467 468 /******************************************************************************* 469 * STM32MP1 IWDG 470 ******************************************************************************/ 471 #define IWDG_MAX_INSTANCE U(2) 472 #define IWDG1_INST U(0) 473 #define IWDG2_INST U(1) 474 475 #define IWDG1_BASE U(0x5C003000) 476 #define IWDG2_BASE U(0x5A002000) 477 478 /******************************************************************************* 479 * Miscellaneous STM32MP1 peripherals base address 480 ******************************************************************************/ 481 #define BSEC_BASE U(0x5C005000) 482 #define CRYP1_BASE U(0x54001000) 483 #define DBGMCU_BASE U(0x50081000) 484 #define HASH1_BASE U(0x54002000) 485 #define I2C4_BASE U(0x5C002000) 486 #define I2C6_BASE U(0x5c009000) 487 #define RNG1_BASE U(0x54003000) 488 #define RTC_BASE U(0x5c004000) 489 #define SPI6_BASE U(0x5c001000) 490 #define STGEN_BASE U(0x5c008000) 491 #define SYSCFG_BASE U(0x50020000) 492 493 /******************************************************************************* 494 * REGULATORS 495 ******************************************************************************/ 496 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 497 #define PLAT_NB_RDEVS U(19) 498 /* 1 FIXED */ 499 #define PLAT_NB_FIXED_REGS U(1) 500 501 /******************************************************************************* 502 * Device Tree defines 503 ******************************************************************************/ 504 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 505 #define DT_DDR_COMPAT "st,stm32mp1-ddr" 506 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 507 #define DT_NVMEM_LAYOUT_COMPAT "st,stm32-nvmem-layout" 508 #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" 509 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 510 #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure" 511 512 #endif /* STM32MP1_DEF_H */ 513