1 /* 2 * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/debug.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/clk.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <drivers/st/stm32mp_clkfunc.h> 20 #include <drivers/st/stm32mp1_clk.h> 21 #include <drivers/st/stm32mp1_rcc.h> 22 #include <dt-bindings/clock/stm32mp1-clksrc.h> 23 #include <lib/mmio.h> 24 #include <lib/spinlock.h> 25 #include <lib/utils_def.h> 26 #include <libfdt.h> 27 #include <plat/common/platform.h> 28 29 #include <platform_def.h> 30 31 #define MAX_HSI_HZ 64000000 32 #define USB_PHY_48_MHZ 48000000 33 34 #define TIMEOUT_US_200MS U(200000) 35 #define TIMEOUT_US_1S U(1000000) 36 37 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 38 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 39 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 40 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 41 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 42 43 const char *stm32mp_osc_node_label[NB_OSC] = { 44 [_LSI] = "clk-lsi", 45 [_LSE] = "clk-lse", 46 [_HSI] = "clk-hsi", 47 [_HSE] = "clk-hse", 48 [_CSI] = "clk-csi", 49 [_I2S_CKIN] = "i2s_ckin", 50 }; 51 52 enum stm32mp1_parent_id { 53 /* Oscillators are defined in enum stm32mp_osc_id */ 54 55 /* Other parent source */ 56 _HSI_KER = NB_OSC, 57 _HSE_KER, 58 _HSE_KER_DIV2, 59 _HSE_RTC, 60 _CSI_KER, 61 _PLL1_P, 62 _PLL1_Q, 63 _PLL1_R, 64 _PLL2_P, 65 _PLL2_Q, 66 _PLL2_R, 67 _PLL3_P, 68 _PLL3_Q, 69 _PLL3_R, 70 _PLL4_P, 71 _PLL4_Q, 72 _PLL4_R, 73 _ACLK, 74 _PCLK1, 75 _PCLK2, 76 _PCLK3, 77 _PCLK4, 78 _PCLK5, 79 _HCLK6, 80 _HCLK2, 81 _CK_PER, 82 _CK_MPU, 83 _CK_MCU, 84 _USB_PHY_48, 85 _PARENT_NB, 86 _UNKNOWN_ID = 0xff, 87 }; 88 89 /* Lists only the parent clock we are interested in */ 90 enum stm32mp1_parent_sel { 91 _I2C12_SEL, 92 _I2C35_SEL, 93 _STGEN_SEL, 94 _I2C46_SEL, 95 _SPI6_SEL, 96 _UART1_SEL, 97 _RNG1_SEL, 98 _UART6_SEL, 99 _UART24_SEL, 100 _UART35_SEL, 101 _UART78_SEL, 102 _SDMMC12_SEL, 103 _SDMMC3_SEL, 104 _QSPI_SEL, 105 _FMC_SEL, 106 _AXIS_SEL, 107 _MCUS_SEL, 108 _USBPHY_SEL, 109 _USBO_SEL, 110 _MPU_SEL, 111 _CKPER_SEL, 112 _RTC_SEL, 113 _PARENT_SEL_NB, 114 _UNKNOWN_SEL = 0xff, 115 }; 116 117 /* State the parent clock ID straight related to a clock */ 118 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 119 [_HSE] = CK_HSE, 120 [_HSI] = CK_HSI, 121 [_CSI] = CK_CSI, 122 [_LSE] = CK_LSE, 123 [_LSI] = CK_LSI, 124 [_I2S_CKIN] = _UNKNOWN_ID, 125 [_USB_PHY_48] = _UNKNOWN_ID, 126 [_HSI_KER] = CK_HSI, 127 [_HSE_KER] = CK_HSE, 128 [_HSE_KER_DIV2] = CK_HSE_DIV2, 129 [_HSE_RTC] = _UNKNOWN_ID, 130 [_CSI_KER] = CK_CSI, 131 [_PLL1_P] = PLL1_P, 132 [_PLL1_Q] = PLL1_Q, 133 [_PLL1_R] = PLL1_R, 134 [_PLL2_P] = PLL2_P, 135 [_PLL2_Q] = PLL2_Q, 136 [_PLL2_R] = PLL2_R, 137 [_PLL3_P] = PLL3_P, 138 [_PLL3_Q] = PLL3_Q, 139 [_PLL3_R] = PLL3_R, 140 [_PLL4_P] = PLL4_P, 141 [_PLL4_Q] = PLL4_Q, 142 [_PLL4_R] = PLL4_R, 143 [_ACLK] = CK_AXI, 144 [_PCLK1] = CK_AXI, 145 [_PCLK2] = CK_AXI, 146 [_PCLK3] = CK_AXI, 147 [_PCLK4] = CK_AXI, 148 [_PCLK5] = CK_AXI, 149 [_CK_PER] = CK_PER, 150 [_CK_MPU] = CK_MPU, 151 [_CK_MCU] = CK_MCU, 152 }; 153 154 static unsigned int clock_id2parent_id(unsigned long id) 155 { 156 unsigned int n; 157 158 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 159 if (parent_id_clock_id[n] == id) { 160 return n; 161 } 162 } 163 164 return _UNKNOWN_ID; 165 } 166 167 enum stm32mp1_pll_id { 168 _PLL1, 169 _PLL2, 170 _PLL3, 171 _PLL4, 172 _PLL_NB 173 }; 174 175 enum stm32mp1_div_id { 176 _DIV_P, 177 _DIV_Q, 178 _DIV_R, 179 _DIV_NB, 180 }; 181 182 enum stm32mp1_clksrc_id { 183 CLKSRC_MPU, 184 CLKSRC_AXI, 185 CLKSRC_MCU, 186 CLKSRC_PLL12, 187 CLKSRC_PLL3, 188 CLKSRC_PLL4, 189 CLKSRC_RTC, 190 CLKSRC_MCO1, 191 CLKSRC_MCO2, 192 CLKSRC_NB 193 }; 194 195 enum stm32mp1_clkdiv_id { 196 CLKDIV_MPU, 197 CLKDIV_AXI, 198 CLKDIV_MCU, 199 CLKDIV_APB1, 200 CLKDIV_APB2, 201 CLKDIV_APB3, 202 CLKDIV_APB4, 203 CLKDIV_APB5, 204 CLKDIV_RTC, 205 CLKDIV_MCO1, 206 CLKDIV_MCO2, 207 CLKDIV_NB 208 }; 209 210 enum stm32mp1_pllcfg { 211 PLLCFG_M, 212 PLLCFG_N, 213 PLLCFG_P, 214 PLLCFG_Q, 215 PLLCFG_R, 216 PLLCFG_O, 217 PLLCFG_NB 218 }; 219 220 enum stm32mp1_pllcsg { 221 PLLCSG_MOD_PER, 222 PLLCSG_INC_STEP, 223 PLLCSG_SSCG_MODE, 224 PLLCSG_NB 225 }; 226 227 enum stm32mp1_plltype { 228 PLL_800, 229 PLL_1600, 230 PLL_TYPE_NB 231 }; 232 233 struct stm32mp1_pll { 234 uint8_t refclk_min; 235 uint8_t refclk_max; 236 uint8_t divn_max; 237 }; 238 239 struct stm32mp1_clk_gate { 240 uint16_t offset; 241 uint8_t bit; 242 uint8_t index; 243 uint8_t set_clr; 244 uint8_t secure; 245 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 246 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 247 }; 248 249 struct stm32mp1_clk_sel { 250 uint16_t offset; 251 uint8_t src; 252 uint8_t msk; 253 uint8_t nb_parent; 254 const uint8_t *parent; 255 }; 256 257 #define REFCLK_SIZE 4 258 struct stm32mp1_clk_pll { 259 enum stm32mp1_plltype plltype; 260 uint16_t rckxselr; 261 uint16_t pllxcfgr1; 262 uint16_t pllxcfgr2; 263 uint16_t pllxfracr; 264 uint16_t pllxcr; 265 uint16_t pllxcsgr; 266 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 267 }; 268 269 /* Clocks with selectable source and non set/clr register access */ 270 #define _CLK_SELEC(sec, off, b, idx, s) \ 271 { \ 272 .offset = (off), \ 273 .bit = (b), \ 274 .index = (idx), \ 275 .set_clr = 0, \ 276 .secure = (sec), \ 277 .sel = (s), \ 278 .fixed = _UNKNOWN_ID, \ 279 } 280 281 /* Clocks with fixed source and non set/clr register access */ 282 #define _CLK_FIXED(sec, off, b, idx, f) \ 283 { \ 284 .offset = (off), \ 285 .bit = (b), \ 286 .index = (idx), \ 287 .set_clr = 0, \ 288 .secure = (sec), \ 289 .sel = _UNKNOWN_SEL, \ 290 .fixed = (f), \ 291 } 292 293 /* Clocks with selectable source and set/clr register access */ 294 #define _CLK_SC_SELEC(sec, off, b, idx, s) \ 295 { \ 296 .offset = (off), \ 297 .bit = (b), \ 298 .index = (idx), \ 299 .set_clr = 1, \ 300 .secure = (sec), \ 301 .sel = (s), \ 302 .fixed = _UNKNOWN_ID, \ 303 } 304 305 /* Clocks with fixed source and set/clr register access */ 306 #define _CLK_SC_FIXED(sec, off, b, idx, f) \ 307 { \ 308 .offset = (off), \ 309 .bit = (b), \ 310 .index = (idx), \ 311 .set_clr = 1, \ 312 .secure = (sec), \ 313 .sel = _UNKNOWN_SEL, \ 314 .fixed = (f), \ 315 } 316 317 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 318 [_ ## _label ## _SEL] = { \ 319 .offset = _rcc_selr, \ 320 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 321 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 322 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 323 .parent = (_parents), \ 324 .nb_parent = ARRAY_SIZE(_parents) \ 325 } 326 327 #define _CLK_PLL(idx, type, off1, off2, off3, \ 328 off4, off5, off6, \ 329 p1, p2, p3, p4) \ 330 [(idx)] = { \ 331 .plltype = (type), \ 332 .rckxselr = (off1), \ 333 .pllxcfgr1 = (off2), \ 334 .pllxcfgr2 = (off3), \ 335 .pllxfracr = (off4), \ 336 .pllxcr = (off5), \ 337 .pllxcsgr = (off6), \ 338 .refclk[0] = (p1), \ 339 .refclk[1] = (p2), \ 340 .refclk[2] = (p3), \ 341 .refclk[3] = (p4), \ 342 } 343 344 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 345 346 #define SEC 1 347 #define N_S 0 348 349 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 350 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 351 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 352 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 353 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 354 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 355 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 356 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 357 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 358 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 359 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 360 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 361 362 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 363 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 364 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 365 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 366 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 367 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 368 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 369 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 370 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 371 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 372 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 373 374 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 375 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 376 377 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 378 379 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 380 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 381 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 382 383 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 384 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 385 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 386 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 387 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 388 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 389 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 390 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 391 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 392 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 393 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 394 395 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 396 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 397 398 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 399 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 400 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 401 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 402 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 403 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 404 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 405 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 406 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 407 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 408 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 409 410 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 411 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 412 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 413 _CLK_SC_SELEC(SEC, RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 414 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 415 416 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 417 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 418 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 419 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 420 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 421 422 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL), 423 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 424 }; 425 426 static const uint8_t i2c12_parents[] = { 427 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 428 }; 429 430 static const uint8_t i2c35_parents[] = { 431 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 432 }; 433 434 static const uint8_t stgen_parents[] = { 435 _HSI_KER, _HSE_KER 436 }; 437 438 static const uint8_t i2c46_parents[] = { 439 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 440 }; 441 442 static const uint8_t spi6_parents[] = { 443 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 444 }; 445 446 static const uint8_t usart1_parents[] = { 447 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 448 }; 449 450 static const uint8_t rng1_parents[] = { 451 _CSI, _PLL4_R, _LSE, _LSI 452 }; 453 454 static const uint8_t uart6_parents[] = { 455 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 456 }; 457 458 static const uint8_t uart234578_parents[] = { 459 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 460 }; 461 462 static const uint8_t sdmmc12_parents[] = { 463 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 464 }; 465 466 static const uint8_t sdmmc3_parents[] = { 467 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 468 }; 469 470 static const uint8_t qspi_parents[] = { 471 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 472 }; 473 474 static const uint8_t fmc_parents[] = { 475 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 476 }; 477 478 static const uint8_t axiss_parents[] = { 479 _HSI, _HSE, _PLL2_P 480 }; 481 482 static const uint8_t mcuss_parents[] = { 483 _HSI, _HSE, _CSI, _PLL3_P 484 }; 485 486 static const uint8_t usbphy_parents[] = { 487 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 488 }; 489 490 static const uint8_t usbo_parents[] = { 491 _PLL4_R, _USB_PHY_48 492 }; 493 494 static const uint8_t mpu_parents[] = { 495 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 496 }; 497 498 static const uint8_t per_parents[] = { 499 _HSI, _HSE, _CSI, 500 }; 501 502 static const uint8_t rtc_parents[] = { 503 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 504 }; 505 506 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 507 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 508 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 509 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 510 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 511 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 512 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 513 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 514 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 515 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents), 516 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 517 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 518 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 519 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 520 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 521 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 522 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 523 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 524 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 525 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents), 526 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents), 527 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 528 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 529 }; 530 531 /* Define characteristic of PLL according type */ 532 #define DIVN_MIN 24 533 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 534 [PLL_800] = { 535 .refclk_min = 4, 536 .refclk_max = 16, 537 .divn_max = 99, 538 }, 539 [PLL_1600] = { 540 .refclk_min = 8, 541 .refclk_max = 16, 542 .divn_max = 199, 543 }, 544 }; 545 546 /* PLLNCFGR2 register divider by output */ 547 static const uint8_t pllncfgr2[_DIV_NB] = { 548 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 549 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 550 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 551 }; 552 553 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 554 _CLK_PLL(_PLL1, PLL_1600, 555 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 556 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 557 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 558 _CLK_PLL(_PLL2, PLL_1600, 559 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 560 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 561 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 562 _CLK_PLL(_PLL3, PLL_800, 563 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 564 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 565 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 566 _CLK_PLL(_PLL4, PLL_800, 567 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 568 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 569 _HSI, _HSE, _CSI, _I2S_CKIN), 570 }; 571 572 /* Prescaler table lookups for clock computation */ 573 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 574 static const uint8_t stm32mp1_mcu_div[16] = { 575 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 576 }; 577 578 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 579 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 580 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 581 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 582 0, 1, 2, 3, 4, 4, 4, 4 583 }; 584 585 /* div = /1 /2 /3 /4 */ 586 static const uint8_t stm32mp1_axi_div[8] = { 587 1, 2, 3, 4, 4, 4, 4, 4 588 }; 589 590 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 591 [_HSI] = "HSI", 592 [_HSE] = "HSE", 593 [_CSI] = "CSI", 594 [_LSI] = "LSI", 595 [_LSE] = "LSE", 596 [_I2S_CKIN] = "I2S_CKIN", 597 [_HSI_KER] = "HSI_KER", 598 [_HSE_KER] = "HSE_KER", 599 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 600 [_HSE_RTC] = "HSE_RTC", 601 [_CSI_KER] = "CSI_KER", 602 [_PLL1_P] = "PLL1_P", 603 [_PLL1_Q] = "PLL1_Q", 604 [_PLL1_R] = "PLL1_R", 605 [_PLL2_P] = "PLL2_P", 606 [_PLL2_Q] = "PLL2_Q", 607 [_PLL2_R] = "PLL2_R", 608 [_PLL3_P] = "PLL3_P", 609 [_PLL3_Q] = "PLL3_Q", 610 [_PLL3_R] = "PLL3_R", 611 [_PLL4_P] = "PLL4_P", 612 [_PLL4_Q] = "PLL4_Q", 613 [_PLL4_R] = "PLL4_R", 614 [_ACLK] = "ACLK", 615 [_PCLK1] = "PCLK1", 616 [_PCLK2] = "PCLK2", 617 [_PCLK3] = "PCLK3", 618 [_PCLK4] = "PCLK4", 619 [_PCLK5] = "PCLK5", 620 [_HCLK6] = "KCLK6", 621 [_HCLK2] = "HCLK2", 622 [_CK_PER] = "CK_PER", 623 [_CK_MPU] = "CK_MPU", 624 [_CK_MCU] = "CK_MCU", 625 [_USB_PHY_48] = "USB_PHY_48", 626 }; 627 628 /* RCC clock device driver private */ 629 static unsigned long stm32mp1_osc[NB_OSC]; 630 static struct spinlock reg_lock; 631 static unsigned int gate_refcounts[NB_GATES]; 632 static struct spinlock refcount_lock; 633 634 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 635 { 636 return &stm32mp1_clk_gate[idx]; 637 } 638 639 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 640 { 641 return &stm32mp1_clk_sel[idx]; 642 } 643 644 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 645 { 646 return &stm32mp1_clk_pll[idx]; 647 } 648 649 static void stm32mp1_clk_lock(struct spinlock *lock) 650 { 651 if (stm32mp_lock_available()) { 652 /* Assume interrupts are masked */ 653 spin_lock(lock); 654 } 655 } 656 657 static void stm32mp1_clk_unlock(struct spinlock *lock) 658 { 659 if (stm32mp_lock_available()) { 660 spin_unlock(lock); 661 } 662 } 663 664 bool stm32mp1_rcc_is_secure(void) 665 { 666 uintptr_t rcc_base = stm32mp_rcc_base(); 667 uint32_t mask = RCC_TZCR_TZEN; 668 669 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 670 } 671 672 bool stm32mp1_rcc_is_mckprot(void) 673 { 674 uintptr_t rcc_base = stm32mp_rcc_base(); 675 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT; 676 677 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 678 } 679 680 void stm32mp1_clk_rcc_regs_lock(void) 681 { 682 stm32mp1_clk_lock(®_lock); 683 } 684 685 void stm32mp1_clk_rcc_regs_unlock(void) 686 { 687 stm32mp1_clk_unlock(®_lock); 688 } 689 690 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 691 { 692 if (idx >= NB_OSC) { 693 return 0; 694 } 695 696 return stm32mp1_osc[idx]; 697 } 698 699 static int stm32mp1_clk_get_gated_id(unsigned long id) 700 { 701 unsigned int i; 702 703 for (i = 0U; i < NB_GATES; i++) { 704 if (gate_ref(i)->index == id) { 705 return i; 706 } 707 } 708 709 ERROR("%s: clk id %lu not found\n", __func__, id); 710 711 return -EINVAL; 712 } 713 714 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 715 { 716 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 717 } 718 719 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 720 { 721 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 722 } 723 724 static int stm32mp1_clk_get_parent(unsigned long id) 725 { 726 const struct stm32mp1_clk_sel *sel; 727 uint32_t p_sel; 728 int i; 729 enum stm32mp1_parent_id p; 730 enum stm32mp1_parent_sel s; 731 uintptr_t rcc_base = stm32mp_rcc_base(); 732 733 /* Few non gateable clock have a static parent ID, find them */ 734 i = (int)clock_id2parent_id(id); 735 if (i != _UNKNOWN_ID) { 736 return i; 737 } 738 739 i = stm32mp1_clk_get_gated_id(id); 740 if (i < 0) { 741 panic(); 742 } 743 744 p = stm32mp1_clk_get_fixed_parent(i); 745 if (p < _PARENT_NB) { 746 return (int)p; 747 } 748 749 s = stm32mp1_clk_get_sel(i); 750 if (s == _UNKNOWN_SEL) { 751 return -EINVAL; 752 } 753 if (s >= _PARENT_SEL_NB) { 754 panic(); 755 } 756 757 sel = clk_sel_ref(s); 758 p_sel = (mmio_read_32(rcc_base + sel->offset) & 759 (sel->msk << sel->src)) >> sel->src; 760 if (p_sel < sel->nb_parent) { 761 return (int)sel->parent[p_sel]; 762 } 763 764 return -EINVAL; 765 } 766 767 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 768 { 769 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 770 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 771 772 return stm32mp1_clk_get_fixed(pll->refclk[src]); 773 } 774 775 /* 776 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 777 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 778 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 779 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 780 */ 781 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 782 { 783 unsigned long refclk, fvco; 784 uint32_t cfgr1, fracr, divm, divn; 785 uintptr_t rcc_base = stm32mp_rcc_base(); 786 787 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 788 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 789 790 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 791 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 792 793 refclk = stm32mp1_pll_get_fref(pll); 794 795 /* 796 * With FRACV : 797 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 798 * Without FRACV 799 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 800 */ 801 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 802 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 803 RCC_PLLNFRACR_FRACV_SHIFT; 804 unsigned long long numerator, denominator; 805 806 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 807 numerator = refclk * numerator; 808 denominator = ((unsigned long long)divm + 1U) << 13; 809 fvco = (unsigned long)(numerator / denominator); 810 } else { 811 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 812 } 813 814 return fvco; 815 } 816 817 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 818 enum stm32mp1_div_id div_id) 819 { 820 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 821 unsigned long dfout; 822 uint32_t cfgr2, divy; 823 824 if (div_id >= _DIV_NB) { 825 return 0; 826 } 827 828 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 829 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 830 831 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 832 833 return dfout; 834 } 835 836 static unsigned long get_clock_rate(int p) 837 { 838 uint32_t reg, clkdiv; 839 unsigned long clock = 0; 840 uintptr_t rcc_base = stm32mp_rcc_base(); 841 842 switch (p) { 843 case _CK_MPU: 844 /* MPU sub system */ 845 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 846 switch (reg & RCC_SELR_SRC_MASK) { 847 case RCC_MPCKSELR_HSI: 848 clock = stm32mp1_clk_get_fixed(_HSI); 849 break; 850 case RCC_MPCKSELR_HSE: 851 clock = stm32mp1_clk_get_fixed(_HSE); 852 break; 853 case RCC_MPCKSELR_PLL: 854 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 855 break; 856 case RCC_MPCKSELR_PLL_MPUDIV: 857 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 858 859 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 860 clkdiv = reg & RCC_MPUDIV_MASK; 861 clock >>= stm32mp1_mpu_div[clkdiv]; 862 break; 863 default: 864 break; 865 } 866 break; 867 /* AXI sub system */ 868 case _ACLK: 869 case _HCLK2: 870 case _HCLK6: 871 case _PCLK4: 872 case _PCLK5: 873 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 874 switch (reg & RCC_SELR_SRC_MASK) { 875 case RCC_ASSCKSELR_HSI: 876 clock = stm32mp1_clk_get_fixed(_HSI); 877 break; 878 case RCC_ASSCKSELR_HSE: 879 clock = stm32mp1_clk_get_fixed(_HSE); 880 break; 881 case RCC_ASSCKSELR_PLL: 882 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 883 break; 884 default: 885 break; 886 } 887 888 /* System clock divider */ 889 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 890 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 891 892 switch (p) { 893 case _PCLK4: 894 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 895 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 896 break; 897 case _PCLK5: 898 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 899 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 900 break; 901 default: 902 break; 903 } 904 break; 905 /* MCU sub system */ 906 case _CK_MCU: 907 case _PCLK1: 908 case _PCLK2: 909 case _PCLK3: 910 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 911 switch (reg & RCC_SELR_SRC_MASK) { 912 case RCC_MSSCKSELR_HSI: 913 clock = stm32mp1_clk_get_fixed(_HSI); 914 break; 915 case RCC_MSSCKSELR_HSE: 916 clock = stm32mp1_clk_get_fixed(_HSE); 917 break; 918 case RCC_MSSCKSELR_CSI: 919 clock = stm32mp1_clk_get_fixed(_CSI); 920 break; 921 case RCC_MSSCKSELR_PLL: 922 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 923 break; 924 default: 925 break; 926 } 927 928 /* MCU clock divider */ 929 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 930 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 931 932 switch (p) { 933 case _PCLK1: 934 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 935 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 936 break; 937 case _PCLK2: 938 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 939 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 940 break; 941 case _PCLK3: 942 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 943 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 944 break; 945 case _CK_MCU: 946 default: 947 break; 948 } 949 break; 950 case _CK_PER: 951 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 952 switch (reg & RCC_SELR_SRC_MASK) { 953 case RCC_CPERCKSELR_HSI: 954 clock = stm32mp1_clk_get_fixed(_HSI); 955 break; 956 case RCC_CPERCKSELR_HSE: 957 clock = stm32mp1_clk_get_fixed(_HSE); 958 break; 959 case RCC_CPERCKSELR_CSI: 960 clock = stm32mp1_clk_get_fixed(_CSI); 961 break; 962 default: 963 break; 964 } 965 break; 966 case _HSI: 967 case _HSI_KER: 968 clock = stm32mp1_clk_get_fixed(_HSI); 969 break; 970 case _CSI: 971 case _CSI_KER: 972 clock = stm32mp1_clk_get_fixed(_CSI); 973 break; 974 case _HSE: 975 case _HSE_KER: 976 clock = stm32mp1_clk_get_fixed(_HSE); 977 break; 978 case _HSE_KER_DIV2: 979 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 980 break; 981 case _HSE_RTC: 982 clock = stm32mp1_clk_get_fixed(_HSE); 983 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U; 984 break; 985 case _LSI: 986 clock = stm32mp1_clk_get_fixed(_LSI); 987 break; 988 case _LSE: 989 clock = stm32mp1_clk_get_fixed(_LSE); 990 break; 991 /* PLL */ 992 case _PLL1_P: 993 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 994 break; 995 case _PLL1_Q: 996 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 997 break; 998 case _PLL1_R: 999 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 1000 break; 1001 case _PLL2_P: 1002 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 1003 break; 1004 case _PLL2_Q: 1005 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 1006 break; 1007 case _PLL2_R: 1008 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 1009 break; 1010 case _PLL3_P: 1011 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1012 break; 1013 case _PLL3_Q: 1014 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1015 break; 1016 case _PLL3_R: 1017 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1018 break; 1019 case _PLL4_P: 1020 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1021 break; 1022 case _PLL4_Q: 1023 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1024 break; 1025 case _PLL4_R: 1026 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1027 break; 1028 /* Other */ 1029 case _USB_PHY_48: 1030 clock = USB_PHY_48_MHZ; 1031 break; 1032 default: 1033 break; 1034 } 1035 1036 return clock; 1037 } 1038 1039 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1040 { 1041 uintptr_t rcc_base = stm32mp_rcc_base(); 1042 1043 VERBOSE("Enable clock %u\n", gate->index); 1044 1045 if (gate->set_clr != 0U) { 1046 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1047 } else { 1048 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1049 } 1050 } 1051 1052 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1053 { 1054 uintptr_t rcc_base = stm32mp_rcc_base(); 1055 1056 VERBOSE("Disable clock %u\n", gate->index); 1057 1058 if (gate->set_clr != 0U) { 1059 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1060 BIT(gate->bit)); 1061 } else { 1062 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1063 } 1064 } 1065 1066 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1067 { 1068 uintptr_t rcc_base = stm32mp_rcc_base(); 1069 1070 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1071 } 1072 1073 /* Oscillators and PLLs are not gated at runtime */ 1074 static bool clock_is_always_on(unsigned long id) 1075 { 1076 switch (id) { 1077 case CK_HSE: 1078 case CK_CSI: 1079 case CK_LSI: 1080 case CK_LSE: 1081 case CK_HSI: 1082 case CK_HSE_DIV2: 1083 case PLL1_Q: 1084 case PLL1_R: 1085 case PLL2_P: 1086 case PLL2_Q: 1087 case PLL2_R: 1088 case PLL3_P: 1089 case PLL3_Q: 1090 case PLL3_R: 1091 case CK_AXI: 1092 case CK_MPU: 1093 case CK_MCU: 1094 case RTC: 1095 return true; 1096 default: 1097 return false; 1098 } 1099 } 1100 1101 static void __stm32mp1_clk_enable(unsigned long id, bool with_refcnt) 1102 { 1103 const struct stm32mp1_clk_gate *gate; 1104 int i; 1105 1106 if (clock_is_always_on(id)) { 1107 return; 1108 } 1109 1110 i = stm32mp1_clk_get_gated_id(id); 1111 if (i < 0) { 1112 ERROR("Clock %lu can't be enabled\n", id); 1113 panic(); 1114 } 1115 1116 gate = gate_ref(i); 1117 1118 if (!with_refcnt) { 1119 __clk_enable(gate); 1120 return; 1121 } 1122 1123 stm32mp1_clk_lock(&refcount_lock); 1124 1125 if (gate_refcounts[i] == 0U) { 1126 __clk_enable(gate); 1127 } 1128 1129 gate_refcounts[i]++; 1130 if (gate_refcounts[i] == UINT_MAX) { 1131 ERROR("Clock %lu refcount reached max value\n", id); 1132 panic(); 1133 } 1134 1135 stm32mp1_clk_unlock(&refcount_lock); 1136 } 1137 1138 static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt) 1139 { 1140 const struct stm32mp1_clk_gate *gate; 1141 int i; 1142 1143 if (clock_is_always_on(id)) { 1144 return; 1145 } 1146 1147 i = stm32mp1_clk_get_gated_id(id); 1148 if (i < 0) { 1149 ERROR("Clock %lu can't be disabled\n", id); 1150 panic(); 1151 } 1152 1153 gate = gate_ref(i); 1154 1155 if (!with_refcnt) { 1156 __clk_disable(gate); 1157 return; 1158 } 1159 1160 stm32mp1_clk_lock(&refcount_lock); 1161 1162 if (gate_refcounts[i] == 0U) { 1163 ERROR("Clock %lu refcount reached 0\n", id); 1164 panic(); 1165 } 1166 gate_refcounts[i]--; 1167 1168 if (gate_refcounts[i] == 0U) { 1169 __clk_disable(gate); 1170 } 1171 1172 stm32mp1_clk_unlock(&refcount_lock); 1173 } 1174 1175 static int stm32mp_clk_enable(unsigned long id) 1176 { 1177 __stm32mp1_clk_enable(id, true); 1178 1179 return 0; 1180 } 1181 1182 static void stm32mp_clk_disable(unsigned long id) 1183 { 1184 __stm32mp1_clk_disable(id, true); 1185 } 1186 1187 static bool stm32mp_clk_is_enabled(unsigned long id) 1188 { 1189 int i; 1190 1191 if (clock_is_always_on(id)) { 1192 return true; 1193 } 1194 1195 i = stm32mp1_clk_get_gated_id(id); 1196 if (i < 0) { 1197 panic(); 1198 } 1199 1200 return __clk_is_enabled(gate_ref(i)); 1201 } 1202 1203 static unsigned long stm32mp_clk_get_rate(unsigned long id) 1204 { 1205 uintptr_t rcc_base = stm32mp_rcc_base(); 1206 int p = stm32mp1_clk_get_parent(id); 1207 uint32_t prescaler, timpre; 1208 unsigned long parent_rate; 1209 1210 if (p < 0) { 1211 return 0; 1212 } 1213 1214 parent_rate = get_clock_rate(p); 1215 1216 switch (id) { 1217 case TIM2_K: 1218 case TIM3_K: 1219 case TIM4_K: 1220 case TIM5_K: 1221 case TIM6_K: 1222 case TIM7_K: 1223 case TIM12_K: 1224 case TIM13_K: 1225 case TIM14_K: 1226 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) & 1227 RCC_APBXDIV_MASK; 1228 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) & 1229 RCC_TIMGXPRER_TIMGXPRE; 1230 break; 1231 1232 case TIM1_K: 1233 case TIM8_K: 1234 case TIM15_K: 1235 case TIM16_K: 1236 case TIM17_K: 1237 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) & 1238 RCC_APBXDIV_MASK; 1239 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) & 1240 RCC_TIMGXPRER_TIMGXPRE; 1241 break; 1242 1243 default: 1244 return parent_rate; 1245 } 1246 1247 if (prescaler == 0U) { 1248 return parent_rate; 1249 } 1250 1251 return parent_rate * (timpre + 1U) * 2U; 1252 } 1253 1254 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1255 { 1256 uintptr_t address = stm32mp_rcc_base() + offset; 1257 1258 if (enable) { 1259 mmio_setbits_32(address, mask_on); 1260 } else { 1261 mmio_clrbits_32(address, mask_on); 1262 } 1263 } 1264 1265 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1266 { 1267 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1268 uintptr_t address = stm32mp_rcc_base() + offset; 1269 1270 mmio_write_32(address, mask_on); 1271 } 1272 1273 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1274 { 1275 uint64_t timeout; 1276 uint32_t mask_test; 1277 uintptr_t address = stm32mp_rcc_base() + offset; 1278 1279 if (enable) { 1280 mask_test = mask_rdy; 1281 } else { 1282 mask_test = 0; 1283 } 1284 1285 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1286 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1287 if (timeout_elapsed(timeout)) { 1288 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1289 mask_rdy, address, enable, mmio_read_32(address)); 1290 return -ETIMEDOUT; 1291 } 1292 } 1293 1294 return 0; 1295 } 1296 1297 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1298 { 1299 uint32_t value; 1300 uintptr_t rcc_base = stm32mp_rcc_base(); 1301 1302 if (digbyp) { 1303 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1304 } 1305 1306 if (bypass || digbyp) { 1307 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1308 } 1309 1310 /* 1311 * Warning: not recommended to switch directly from "high drive" 1312 * to "medium low drive", and vice-versa. 1313 */ 1314 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1315 RCC_BDCR_LSEDRV_SHIFT; 1316 1317 while (value != lsedrv) { 1318 if (value > lsedrv) { 1319 value--; 1320 } else { 1321 value++; 1322 } 1323 1324 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1325 RCC_BDCR_LSEDRV_MASK, 1326 value << RCC_BDCR_LSEDRV_SHIFT); 1327 } 1328 1329 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1330 } 1331 1332 static void stm32mp1_lse_wait(void) 1333 { 1334 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1335 VERBOSE("%s: failed\n", __func__); 1336 } 1337 } 1338 1339 static void stm32mp1_lsi_set(bool enable) 1340 { 1341 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1342 1343 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1344 VERBOSE("%s: failed\n", __func__); 1345 } 1346 } 1347 1348 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1349 { 1350 uintptr_t rcc_base = stm32mp_rcc_base(); 1351 1352 if (digbyp) { 1353 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1354 } 1355 1356 if (bypass || digbyp) { 1357 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1358 } 1359 1360 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1361 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1362 VERBOSE("%s: failed\n", __func__); 1363 } 1364 1365 if (css) { 1366 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1367 } 1368 1369 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 1370 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) && 1371 (!(digbyp || bypass))) { 1372 panic(); 1373 } 1374 #endif 1375 } 1376 1377 static void stm32mp1_csi_set(bool enable) 1378 { 1379 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1380 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1381 VERBOSE("%s: failed\n", __func__); 1382 } 1383 } 1384 1385 static void stm32mp1_hsi_set(bool enable) 1386 { 1387 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1388 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1389 VERBOSE("%s: failed\n", __func__); 1390 } 1391 } 1392 1393 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1394 { 1395 uint64_t timeout; 1396 uintptr_t rcc_base = stm32mp_rcc_base(); 1397 uintptr_t address = rcc_base + RCC_OCRDYR; 1398 1399 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1400 RCC_HSICFGR_HSIDIV_MASK, 1401 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1402 1403 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1404 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1405 if (timeout_elapsed(timeout)) { 1406 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1407 address, mmio_read_32(address)); 1408 return -ETIMEDOUT; 1409 } 1410 } 1411 1412 return 0; 1413 } 1414 1415 static int stm32mp1_hsidiv(unsigned long hsifreq) 1416 { 1417 uint8_t hsidiv; 1418 uint32_t hsidivfreq = MAX_HSI_HZ; 1419 1420 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1421 if (hsidivfreq == hsifreq) { 1422 break; 1423 } 1424 1425 hsidivfreq /= 2U; 1426 } 1427 1428 if (hsidiv == 4U) { 1429 ERROR("Invalid clk-hsi frequency\n"); 1430 return -1; 1431 } 1432 1433 if (hsidiv != 0U) { 1434 return stm32mp1_set_hsidiv(hsidiv); 1435 } 1436 1437 return 0; 1438 } 1439 1440 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1441 unsigned int clksrc, 1442 uint32_t *pllcfg, int plloff) 1443 { 1444 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1445 uintptr_t rcc_base = stm32mp_rcc_base(); 1446 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1447 enum stm32mp1_plltype type = pll->plltype; 1448 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1449 unsigned long refclk; 1450 uint32_t ifrge = 0U; 1451 uint32_t src, value, fracv = 0; 1452 void *fdt; 1453 1454 /* Check PLL output */ 1455 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1456 return false; 1457 } 1458 1459 /* Check current clksrc */ 1460 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1461 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1462 return false; 1463 } 1464 1465 /* Check Div */ 1466 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1467 1468 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1469 (pllcfg[PLLCFG_M] + 1U); 1470 1471 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1472 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1473 return false; 1474 } 1475 1476 if ((type == PLL_800) && (refclk >= 8000000U)) { 1477 ifrge = 1U; 1478 } 1479 1480 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1481 RCC_PLLNCFGR1_DIVN_MASK; 1482 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1483 RCC_PLLNCFGR1_DIVM_MASK; 1484 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1485 RCC_PLLNCFGR1_IFRGE_MASK; 1486 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1487 return false; 1488 } 1489 1490 /* Fractional configuration */ 1491 if (fdt_get_address(&fdt) == 1) { 1492 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1493 } 1494 1495 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1496 value |= RCC_PLLNFRACR_FRACLE; 1497 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1498 return false; 1499 } 1500 1501 /* Output config */ 1502 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1503 RCC_PLLNCFGR2_DIVP_MASK; 1504 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1505 RCC_PLLNCFGR2_DIVQ_MASK; 1506 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1507 RCC_PLLNCFGR2_DIVR_MASK; 1508 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1509 return false; 1510 } 1511 1512 return true; 1513 } 1514 1515 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1516 { 1517 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1518 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1519 1520 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1521 mmio_clrsetbits_32(pllxcr, 1522 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1523 RCC_PLLNCR_DIVREN, 1524 RCC_PLLNCR_PLLON); 1525 } 1526 1527 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1528 { 1529 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1530 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1531 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1532 1533 /* Wait PLL lock */ 1534 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1535 if (timeout_elapsed(timeout)) { 1536 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1537 pll_id, pllxcr, mmio_read_32(pllxcr)); 1538 return -ETIMEDOUT; 1539 } 1540 } 1541 1542 /* Start the requested output */ 1543 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1544 1545 return 0; 1546 } 1547 1548 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1549 { 1550 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1551 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1552 uint64_t timeout; 1553 1554 /* Stop all output */ 1555 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1556 RCC_PLLNCR_DIVREN); 1557 1558 /* Stop PLL */ 1559 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1560 1561 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1562 /* Wait PLL stopped */ 1563 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1564 if (timeout_elapsed(timeout)) { 1565 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1566 pll_id, pllxcr, mmio_read_32(pllxcr)); 1567 return -ETIMEDOUT; 1568 } 1569 } 1570 1571 return 0; 1572 } 1573 1574 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1575 uint32_t *pllcfg) 1576 { 1577 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1578 uintptr_t rcc_base = stm32mp_rcc_base(); 1579 uint32_t value; 1580 1581 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1582 RCC_PLLNCFGR2_DIVP_MASK; 1583 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1584 RCC_PLLNCFGR2_DIVQ_MASK; 1585 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1586 RCC_PLLNCFGR2_DIVR_MASK; 1587 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1588 } 1589 1590 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1591 uint32_t *pllcfg, uint32_t fracv) 1592 { 1593 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1594 uintptr_t rcc_base = stm32mp_rcc_base(); 1595 enum stm32mp1_plltype type = pll->plltype; 1596 unsigned long refclk; 1597 uint32_t ifrge = 0; 1598 uint32_t src, value; 1599 1600 src = mmio_read_32(rcc_base + pll->rckxselr) & 1601 RCC_SELR_REFCLK_SRC_MASK; 1602 1603 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1604 (pllcfg[PLLCFG_M] + 1U); 1605 1606 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1607 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1608 return -EINVAL; 1609 } 1610 1611 if ((type == PLL_800) && (refclk >= 8000000U)) { 1612 ifrge = 1U; 1613 } 1614 1615 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1616 RCC_PLLNCFGR1_DIVN_MASK; 1617 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1618 RCC_PLLNCFGR1_DIVM_MASK; 1619 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1620 RCC_PLLNCFGR1_IFRGE_MASK; 1621 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1622 1623 /* Fractional configuration */ 1624 value = 0; 1625 mmio_write_32(rcc_base + pll->pllxfracr, value); 1626 1627 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1628 mmio_write_32(rcc_base + pll->pllxfracr, value); 1629 1630 value |= RCC_PLLNFRACR_FRACLE; 1631 mmio_write_32(rcc_base + pll->pllxfracr, value); 1632 1633 stm32mp1_pll_config_output(pll_id, pllcfg); 1634 1635 return 0; 1636 } 1637 1638 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1639 { 1640 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1641 uint32_t pllxcsg = 0; 1642 1643 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1644 RCC_PLLNCSGR_MOD_PER_MASK; 1645 1646 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1647 RCC_PLLNCSGR_INC_STEP_MASK; 1648 1649 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1650 RCC_PLLNCSGR_SSCG_MODE_MASK; 1651 1652 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1653 1654 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1655 RCC_PLLNCR_SSCG_CTRL); 1656 } 1657 1658 static int stm32mp1_set_clksrc(unsigned int clksrc) 1659 { 1660 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1661 uint64_t timeout; 1662 1663 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1664 clksrc & RCC_SELR_SRC_MASK); 1665 1666 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1667 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1668 if (timeout_elapsed(timeout)) { 1669 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1670 clksrc_address, mmio_read_32(clksrc_address)); 1671 return -ETIMEDOUT; 1672 } 1673 } 1674 1675 return 0; 1676 } 1677 1678 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1679 { 1680 uint64_t timeout; 1681 1682 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1683 clkdiv & RCC_DIVR_DIV_MASK); 1684 1685 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1686 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1687 if (timeout_elapsed(timeout)) { 1688 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1689 clkdiv, address, mmio_read_32(address)); 1690 return -ETIMEDOUT; 1691 } 1692 } 1693 1694 return 0; 1695 } 1696 1697 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1698 { 1699 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1700 1701 /* 1702 * Binding clksrc : 1703 * bit15-4 offset 1704 * bit3: disable 1705 * bit2-0: MCOSEL[2:0] 1706 */ 1707 if ((clksrc & 0x8U) != 0U) { 1708 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1709 } else { 1710 mmio_clrsetbits_32(clksrc_address, 1711 RCC_MCOCFG_MCOSRC_MASK, 1712 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1713 mmio_clrsetbits_32(clksrc_address, 1714 RCC_MCOCFG_MCODIV_MASK, 1715 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1716 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1717 } 1718 } 1719 1720 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1721 { 1722 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1723 1724 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1725 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1726 mmio_clrsetbits_32(address, 1727 RCC_BDCR_RTCSRC_MASK, 1728 (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); 1729 1730 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1731 } 1732 1733 if (lse_css) { 1734 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1735 } 1736 } 1737 1738 static void stm32mp1_stgen_config(void) 1739 { 1740 uint32_t cntfid0; 1741 unsigned long rate; 1742 unsigned long long counter; 1743 1744 cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF); 1745 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1746 1747 if (cntfid0 == rate) { 1748 return; 1749 } 1750 1751 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1752 counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1753 counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32; 1754 counter = (counter * rate / cntfid0); 1755 1756 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); 1757 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1758 mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); 1759 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1760 1761 write_cntfrq((u_register_t)rate); 1762 1763 /* Need to update timer with new frequency */ 1764 generic_delay_timer_init(); 1765 } 1766 1767 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1768 { 1769 unsigned long long cnt; 1770 1771 cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) | 1772 mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1773 1774 cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U; 1775 1776 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1777 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt); 1778 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1779 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1780 } 1781 1782 static void stm32mp1_pkcs_config(uint32_t pkcs) 1783 { 1784 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1785 uint32_t value = pkcs & 0xFU; 1786 uint32_t mask = 0xFU; 1787 1788 if ((pkcs & BIT(31)) != 0U) { 1789 mask <<= 4; 1790 value <<= 4; 1791 } 1792 1793 mmio_clrsetbits_32(address, mask, value); 1794 } 1795 1796 static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg, 1797 uint32_t *fracv, uint32_t *csg, 1798 bool *csg_set) 1799 { 1800 void *fdt; 1801 int ret; 1802 1803 if (fdt_get_address(&fdt) == 0) { 1804 return -FDT_ERR_NOTFOUND; 1805 } 1806 1807 ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB, 1808 pllcfg); 1809 if (ret < 0) { 1810 return -FDT_ERR_NOTFOUND; 1811 } 1812 1813 *fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1814 1815 ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB, 1816 csg); 1817 1818 *csg_set = (ret == 0); 1819 1820 if (ret == -FDT_ERR_NOTFOUND) { 1821 ret = 0; 1822 } 1823 1824 return ret; 1825 } 1826 1827 int stm32mp1_clk_init(void) 1828 { 1829 uintptr_t rcc_base = stm32mp_rcc_base(); 1830 uint32_t pllfracv[_PLL_NB]; 1831 uint32_t pllcsg[_PLL_NB][PLLCSG_NB]; 1832 unsigned int clksrc[CLKSRC_NB]; 1833 unsigned int clkdiv[CLKDIV_NB]; 1834 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1835 int plloff[_PLL_NB]; 1836 int ret, len; 1837 enum stm32mp1_pll_id i; 1838 bool pllcsg_set[_PLL_NB]; 1839 bool pllcfg_valid[_PLL_NB]; 1840 bool lse_css = false; 1841 bool pll3_preserve = false; 1842 bool pll4_preserve = false; 1843 bool pll4_bootrom = false; 1844 const fdt32_t *pkcs_cell; 1845 void *fdt; 1846 int stgen_p = stm32mp1_clk_get_parent(STGEN_K); 1847 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K); 1848 1849 if (fdt_get_address(&fdt) == 0) { 1850 return -FDT_ERR_NOTFOUND; 1851 } 1852 1853 /* Check status field to disable security */ 1854 if (!fdt_get_rcc_secure_status()) { 1855 mmio_write_32(rcc_base + RCC_TZCR, 0); 1856 } 1857 1858 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1859 clksrc); 1860 if (ret < 0) { 1861 return -FDT_ERR_NOTFOUND; 1862 } 1863 1864 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1865 clkdiv); 1866 if (ret < 0) { 1867 return -FDT_ERR_NOTFOUND; 1868 } 1869 1870 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1871 char name[12]; 1872 1873 snprintf(name, sizeof(name), "st,pll@%d", i); 1874 plloff[i] = fdt_rcc_subnode_offset(name); 1875 1876 pllcfg_valid[i] = fdt_check_node(plloff[i]); 1877 if (!pllcfg_valid[i]) { 1878 continue; 1879 } 1880 1881 ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i], 1882 &pllfracv[i], pllcsg[i], 1883 &pllcsg_set[i]); 1884 if (ret != 0) { 1885 return ret; 1886 } 1887 } 1888 1889 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1890 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1891 1892 /* 1893 * Switch ON oscillator found in device-tree. 1894 * Note: HSI already ON after BootROM stage. 1895 */ 1896 if (stm32mp1_osc[_LSI] != 0U) { 1897 stm32mp1_lsi_set(true); 1898 } 1899 if (stm32mp1_osc[_LSE] != 0U) { 1900 const char *name = stm32mp_osc_node_label[_LSE]; 1901 bool bypass, digbyp; 1902 uint32_t lsedrv; 1903 1904 bypass = fdt_clk_read_bool(name, "st,bypass"); 1905 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 1906 lse_css = fdt_clk_read_bool(name, "st,css"); 1907 lsedrv = fdt_clk_read_uint32_default(name, "st,drive", 1908 LSEDRV_MEDIUM_HIGH); 1909 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1910 } 1911 if (stm32mp1_osc[_HSE] != 0U) { 1912 const char *name = stm32mp_osc_node_label[_HSE]; 1913 bool bypass, digbyp, css; 1914 1915 bypass = fdt_clk_read_bool(name, "st,bypass"); 1916 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 1917 css = fdt_clk_read_bool(name, "st,css"); 1918 stm32mp1_hse_enable(bypass, digbyp, css); 1919 } 1920 /* 1921 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1922 * => switch on CSI even if node is not present in device tree 1923 */ 1924 stm32mp1_csi_set(true); 1925 1926 /* Come back to HSI */ 1927 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1928 if (ret != 0) { 1929 return ret; 1930 } 1931 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1932 if (ret != 0) { 1933 return ret; 1934 } 1935 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1936 if (ret != 0) { 1937 return ret; 1938 } 1939 1940 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1941 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1942 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1943 clksrc[CLKSRC_PLL3], 1944 pllcfg[_PLL3], 1945 plloff[_PLL3]); 1946 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1947 clksrc[CLKSRC_PLL4], 1948 pllcfg[_PLL4], 1949 plloff[_PLL4]); 1950 } 1951 /* Don't initialize PLL4, when used by BOOTROM */ 1952 if ((stm32mp_get_boot_itf_selected() == 1953 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && 1954 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) { 1955 pll4_bootrom = true; 1956 pll4_preserve = true; 1957 } 1958 1959 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1960 if (((i == _PLL3) && pll3_preserve) || 1961 ((i == _PLL4) && pll4_preserve)) { 1962 continue; 1963 } 1964 1965 ret = stm32mp1_pll_stop(i); 1966 if (ret != 0) { 1967 return ret; 1968 } 1969 } 1970 1971 /* Configure HSIDIV */ 1972 if (stm32mp1_osc[_HSI] != 0U) { 1973 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1974 if (ret != 0) { 1975 return ret; 1976 } 1977 stm32mp1_stgen_config(); 1978 } 1979 1980 /* Select DIV */ 1981 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1982 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1983 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1984 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1985 if (ret != 0) { 1986 return ret; 1987 } 1988 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1989 if (ret != 0) { 1990 return ret; 1991 } 1992 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1993 if (ret != 0) { 1994 return ret; 1995 } 1996 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1997 if (ret != 0) { 1998 return ret; 1999 } 2000 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 2001 if (ret != 0) { 2002 return ret; 2003 } 2004 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 2005 if (ret != 0) { 2006 return ret; 2007 } 2008 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 2009 if (ret != 0) { 2010 return ret; 2011 } 2012 2013 /* No ready bit for RTC */ 2014 mmio_write_32(rcc_base + RCC_RTCDIVR, 2015 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 2016 2017 /* Configure PLLs source */ 2018 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 2019 if (ret != 0) { 2020 return ret; 2021 } 2022 2023 if (!pll3_preserve) { 2024 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 2025 if (ret != 0) { 2026 return ret; 2027 } 2028 } 2029 2030 if (!pll4_preserve) { 2031 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 2032 if (ret != 0) { 2033 return ret; 2034 } 2035 } 2036 2037 /* Configure and start PLLs */ 2038 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2039 if (((i == _PLL3) && pll3_preserve) || 2040 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 2041 continue; 2042 } 2043 2044 if (!pllcfg_valid[i]) { 2045 continue; 2046 } 2047 2048 if ((i == _PLL4) && pll4_bootrom) { 2049 /* Set output divider if not done by the Bootrom */ 2050 stm32mp1_pll_config_output(i, pllcfg[i]); 2051 continue; 2052 } 2053 2054 ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]); 2055 if (ret != 0) { 2056 return ret; 2057 } 2058 2059 if (pllcsg_set[i]) { 2060 stm32mp1_pll_csg(i, pllcsg[i]); 2061 } 2062 2063 stm32mp1_pll_start(i); 2064 } 2065 /* Wait and start PLLs ouptut when ready */ 2066 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2067 if (!pllcfg_valid[i]) { 2068 continue; 2069 } 2070 2071 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 2072 if (ret != 0) { 2073 return ret; 2074 } 2075 } 2076 /* Wait LSE ready before to use it */ 2077 if (stm32mp1_osc[_LSE] != 0U) { 2078 stm32mp1_lse_wait(); 2079 } 2080 2081 /* Configure with expected clock source */ 2082 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 2083 if (ret != 0) { 2084 return ret; 2085 } 2086 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 2087 if (ret != 0) { 2088 return ret; 2089 } 2090 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 2091 if (ret != 0) { 2092 return ret; 2093 } 2094 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 2095 2096 /* Configure PKCK */ 2097 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 2098 if (pkcs_cell != NULL) { 2099 bool ckper_disabled = false; 2100 uint32_t j; 2101 uint32_t usbreg_bootrom = 0U; 2102 2103 if (pll4_bootrom) { 2104 usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR); 2105 } 2106 2107 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 2108 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 2109 2110 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 2111 ckper_disabled = true; 2112 continue; 2113 } 2114 stm32mp1_pkcs_config(pkcs); 2115 } 2116 2117 /* 2118 * CKPER is source for some peripheral clocks 2119 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2120 * only if previous clock is still ON 2121 * => deactivated CKPER only after switching clock 2122 */ 2123 if (ckper_disabled) { 2124 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 2125 } 2126 2127 if (pll4_bootrom) { 2128 uint32_t usbreg_value, usbreg_mask; 2129 const struct stm32mp1_clk_sel *sel; 2130 2131 sel = clk_sel_ref(_USBPHY_SEL); 2132 usbreg_mask = (uint32_t)sel->msk << sel->src; 2133 sel = clk_sel_ref(_USBO_SEL); 2134 usbreg_mask |= (uint32_t)sel->msk << sel->src; 2135 2136 usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) & 2137 usbreg_mask; 2138 usbreg_bootrom &= usbreg_mask; 2139 if (usbreg_bootrom != usbreg_value) { 2140 VERBOSE("forbidden new USB clk path\n"); 2141 VERBOSE("vs bootrom on USB boot\n"); 2142 return -FDT_ERR_BADVALUE; 2143 } 2144 } 2145 } 2146 2147 /* Switch OFF HSI if not found in device-tree */ 2148 if (stm32mp1_osc[_HSI] == 0U) { 2149 stm32mp1_hsi_set(false); 2150 } 2151 stm32mp1_stgen_config(); 2152 2153 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2154 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 2155 RCC_DDRITFCR_DDRCKMOD_MASK, 2156 RCC_DDRITFCR_DDRCKMOD_SSR << 2157 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2158 2159 return 0; 2160 } 2161 2162 static void stm32mp1_osc_clk_init(const char *name, 2163 enum stm32mp_osc_id index) 2164 { 2165 uint32_t frequency; 2166 2167 if (fdt_osc_read_freq(name, &frequency) == 0) { 2168 stm32mp1_osc[index] = frequency; 2169 } 2170 } 2171 2172 static void stm32mp1_osc_init(void) 2173 { 2174 enum stm32mp_osc_id i; 2175 2176 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2177 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2178 } 2179 } 2180 2181 #ifdef STM32MP_SHARED_RESOURCES 2182 /* 2183 * Get the parent ID of the target parent clock, for tagging as secure 2184 * shared clock dependencies. 2185 */ 2186 static int get_parent_id_parent(unsigned int parent_id) 2187 { 2188 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2189 enum stm32mp1_pll_id pll_id; 2190 uint32_t p_sel; 2191 uintptr_t rcc_base = stm32mp_rcc_base(); 2192 2193 switch (parent_id) { 2194 case _ACLK: 2195 case _PCLK4: 2196 case _PCLK5: 2197 s = _AXIS_SEL; 2198 break; 2199 case _PLL1_P: 2200 case _PLL1_Q: 2201 case _PLL1_R: 2202 pll_id = _PLL1; 2203 break; 2204 case _PLL2_P: 2205 case _PLL2_Q: 2206 case _PLL2_R: 2207 pll_id = _PLL2; 2208 break; 2209 case _PLL3_P: 2210 case _PLL3_Q: 2211 case _PLL3_R: 2212 pll_id = _PLL3; 2213 break; 2214 case _PLL4_P: 2215 case _PLL4_Q: 2216 case _PLL4_R: 2217 pll_id = _PLL4; 2218 break; 2219 case _PCLK1: 2220 case _PCLK2: 2221 case _HCLK2: 2222 case _HCLK6: 2223 case _CK_PER: 2224 case _CK_MPU: 2225 case _CK_MCU: 2226 case _USB_PHY_48: 2227 /* We do not expect to access these */ 2228 panic(); 2229 break; 2230 default: 2231 /* Other parents have no parent */ 2232 return -1; 2233 } 2234 2235 if (s != _UNKNOWN_SEL) { 2236 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2237 2238 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2239 sel->msk; 2240 2241 if (p_sel < sel->nb_parent) { 2242 return (int)sel->parent[p_sel]; 2243 } 2244 } else { 2245 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2246 2247 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2248 RCC_SELR_REFCLK_SRC_MASK; 2249 2250 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2251 return (int)pll->refclk[p_sel]; 2252 } 2253 } 2254 2255 VERBOSE("No parent selected for %s\n", 2256 stm32mp1_clk_parent_name[parent_id]); 2257 2258 return -1; 2259 } 2260 2261 static void secure_parent_clocks(unsigned long parent_id) 2262 { 2263 int grandparent_id; 2264 2265 switch (parent_id) { 2266 case _PLL3_P: 2267 case _PLL3_Q: 2268 case _PLL3_R: 2269 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2270 break; 2271 2272 /* These clocks are always secure when RCC is secure */ 2273 case _ACLK: 2274 case _HCLK2: 2275 case _HCLK6: 2276 case _PCLK4: 2277 case _PCLK5: 2278 case _PLL1_P: 2279 case _PLL1_Q: 2280 case _PLL1_R: 2281 case _PLL2_P: 2282 case _PLL2_Q: 2283 case _PLL2_R: 2284 case _HSI: 2285 case _HSI_KER: 2286 case _LSI: 2287 case _CSI: 2288 case _CSI_KER: 2289 case _HSE: 2290 case _HSE_KER: 2291 case _HSE_KER_DIV2: 2292 case _HSE_RTC: 2293 case _LSE: 2294 break; 2295 2296 default: 2297 VERBOSE("Cannot secure parent clock %s\n", 2298 stm32mp1_clk_parent_name[parent_id]); 2299 panic(); 2300 } 2301 2302 grandparent_id = get_parent_id_parent(parent_id); 2303 if (grandparent_id >= 0) { 2304 secure_parent_clocks(grandparent_id); 2305 } 2306 } 2307 2308 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2309 { 2310 int parent_id; 2311 2312 if (!stm32mp1_rcc_is_secure()) { 2313 return; 2314 } 2315 2316 switch (clock_id) { 2317 case PLL1: 2318 case PLL2: 2319 /* PLL1/PLL2 are always secure: nothing to do */ 2320 break; 2321 case PLL3: 2322 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2323 break; 2324 case PLL4: 2325 ERROR("PLL4 cannot be secured\n"); 2326 panic(); 2327 break; 2328 default: 2329 /* Others are expected gateable clock */ 2330 parent_id = stm32mp1_clk_get_parent(clock_id); 2331 if (parent_id < 0) { 2332 INFO("No parent found for clock %lu\n", clock_id); 2333 } else { 2334 secure_parent_clocks(parent_id); 2335 } 2336 break; 2337 } 2338 } 2339 #endif /* STM32MP_SHARED_RESOURCES */ 2340 2341 static void sync_earlyboot_clocks_state(void) 2342 { 2343 unsigned int idx; 2344 const unsigned long secure_enable[] = { 2345 AXIDCG, 2346 BSEC, 2347 DDRC1, DDRC1LP, 2348 DDRC2, DDRC2LP, 2349 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2350 DDRPHYC, DDRPHYCLP, 2351 RTCAPB, 2352 TZC1, TZC2, 2353 TZPC, 2354 STGEN_K, 2355 }; 2356 2357 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2358 stm32mp_clk_enable(secure_enable[idx]); 2359 } 2360 } 2361 2362 static const struct clk_ops stm32mp_clk_ops = { 2363 .enable = stm32mp_clk_enable, 2364 .disable = stm32mp_clk_disable, 2365 .is_enabled = stm32mp_clk_is_enabled, 2366 .get_rate = stm32mp_clk_get_rate, 2367 .get_parent = stm32mp1_clk_get_parent, 2368 }; 2369 2370 int stm32mp1_clk_probe(void) 2371 { 2372 stm32mp1_osc_init(); 2373 2374 sync_earlyboot_clocks_state(); 2375 2376 clk_register(&stm32mp_clk_ops); 2377 2378 return 0; 2379 } 2380