feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(nxp-clk): function parameter should not be modified

The function 'update_stack_depth' modifies the value of the 'depth'
parameter passed by reference. Typically, the caller recevies this
paramet

fix(nxp-clk): function parameter should not be modified

The function 'update_stack_depth' modifies the value of the 'depth'
parameter passed by reference. Typically, the caller recevies this
parameter by value, and it is then passed to 'update_stack_depth' by
reference. This violates MISRA 17.8 rule. To address this issue, a new
local variable is introduced to store the value of 'depth'.

Change-Id: Ia37f4ede9e6558f778bdda17b7b195f1f50d0c30
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): enable the DDR clock

Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.

Change-Id: Idfed24b3e74a189df87

feat(nxp-clk): enable the DDR clock

Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.

Change-Id: Idfed24b3e74a189df87f9782886a91b906cd2022
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add objects needed for DDR clock

The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition

feat(nxp-clk): add objects needed for DDR clock

The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition 0, is also connected to this IP block. Therefore, all the
dependencies mentioned above must be configured to have a working clock.

Change-Id: Ia841428db9acb95c59ea851b6afeb0b7ff9230a2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi

feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add MC_ME utilities

MC_ME is one of the leading hardware blocks responsible for partitions'
transition to and from a reset state. Not being the only one involved in
this role, it must

feat(nxp-clk): add MC_ME utilities

MC_ME is one of the leading hardware blocks responsible for partitions'
transition to and from a reset state. Not being the only one involved in
this role, it must cooperate with some other modules (MC_RGM, RDC) to
successfully bring a peripheral out of the reset state. As a result, the
partition management is isolated into a dedicated file, as parts of it
will later contribute to peripheral reset control.

Change-Id: I6a9dbf28008b1677bc847bbafa474b489c999d05
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add partition reset utilities

MC_RGM is a hardware block involved in resetting peripherals and
partitions. Here, the accessories for partition reset are added.

Change-Id: If00755fe0e

feat(nxp-clk): add partition reset utilities

MC_RGM is a hardware block involved in resetting peripherals and
partitions. Here, the accessories for partition reset are added.

Change-Id: If00755fe0e93ba2e4841f95ed5ae3c87db20bebf
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(s32g274a): workaround for ERR051700 erratum

ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneo

fix(s32g274a): workaround for ERR051700 erratum

ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneously, may cause a false error in the fault control
unit.

The workaround is to clear the SRD resets sequentially instead of
simultaneously.

Change-Id: I883bc223bf6834907259e6964a5702d7186e4c7f
Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): refactor clock enablement

Simplify the clock enablement mechanism from a usage perspective. With
this new approach, enabling a clock cascades the turn-on sequence of all
its parent cl

feat(nxp-clk): refactor clock enablement

Simplify the clock enablement mechanism from a usage perspective. With
this new approach, enabling a clock cascades the turn-on sequence of all
its parent clocks in the clock tree. Therefore, enabling the A53 clock
will also turn on the A53 PLL and the oscillator that feeds it.

Change-Id: Ifc2bee3e9edbb4baced34f9e809a961562f7d0a6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_parent callback

Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type

feat(nxp-clk): add get_parent callback

Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type. Usually, this is determined based on the parent
field, but not always.

Change-Id: I76a3d2636dc23ba2d547d058b8650dd0e99fe1fa
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(nxp-clk): broken UART clock initalization

The UART clock initialization failed because the clock mux enablement
mechanism did not correctly recognize the PERIPH PLL mux. Therefore, it
was report

fix(nxp-clk): broken UART clock initalization

The UART clock initialization failed because the clock mux enablement
mechanism did not correctly recognize the PERIPH PLL mux. Therefore, it
was reported as an unknown mux ID.

Change-Id: I6cc72c87a8462a2ed2e7c360f59a74961bb2f3a1
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz

feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.

Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or

feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or FXOSC oscillators. It has eight outputs (PHIs) and
their frequencies can be controlled programmatically using output
dividers. An additional output clocks the PERIPH DFS using the VCO
frequency of the PERIPH PLL.

Change-Id: I637294b2da94f35e95dc1750dad36c129a276bb9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): enable the XBAR clock

Enable the XBAR clock, which is the primary system clock.

Change-Id: Idaafbb8894472b10e1ed8a35b25967c82106e667
Signed-off-by: Ghennadi Procopciuc <ghennadi.proc

feat(nxp-clk): enable the XBAR clock

Enable the XBAR clock, which is the primary system clock.

Change-Id: Idaafbb8894472b10e1ed8a35b25967c82106e667
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add dependencies for the XBAR clock

Add all clock modules required to enable the XBAR clock, including the
DFS, its output dividers and MC_CGM muxes.

Change-Id: Ib9cf82c0e40b76863637

feat(nxp-clk): add dependencies for the XBAR clock

Add all clock modules required to enable the XBAR clock, including the
DFS, its output dividers and MC_CGM muxes.

Change-Id: Ib9cf82c0e40b76863637ed7602c3a09411d17615
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add CGM0 instance

Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.

Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procop

feat(nxp-clk): add CGM0 instance

Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.

Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add DFS module enablement

Implement enable and set_module_rate callbacks for DFS modules.

Change-Id: Ic9d6034ac04adbabd8fc782aea94ce252439f136
Signed-off-by: Ghennadi Procopciuc <ghe

feat(nxp-clk): add DFS module enablement

Implement enable and set_module_rate callbacks for DFS modules.

Change-Id: Ic9d6034ac04adbabd8fc782aea94ce252439f136
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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refactor(nxp-clk): organize early clocks in groups

This reduces the length of the s32cc_init_early_clks function and offers
space for more early clocks to be added.

Change-Id: I0d11b97779433a6b15cd

refactor(nxp-clk): organize early clocks in groups

This reduces the length of the s32cc_init_early_clks function and offers
space for more early clocks to be added.

Change-Id: I0d11b97779433a6b15cd76c36aefbb7b92381067
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): enable the A53 clock

Enable the A53 clock at 1GHz, the maximum frequency on S32G2 SoCs.

Change-Id: Ife96792faf8f3f46965bdcf4df75fcca5e39dc6e
Signed-off-by: Ghennadi Procopciuc <ghenn

feat(nxp-clk): enable the A53 clock

Enable the A53 clock at 1GHz, the maximum frequency on S32G2 SoCs.

Change-Id: Ife96792faf8f3f46965bdcf4df75fcca5e39dc6e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add ARM PLL ODIV enablement

Enable the PLL dividers using their memory-mapped interface. Otherwise,
the clock will not be propagated to downstream clock modules.

Change-Id: I39115cb2

feat(nxp-clk): add ARM PLL ODIV enablement

Enable the PLL dividers using their memory-mapped interface. Otherwise,
the clock will not be propagated to downstream clock modules.

Change-Id: I39115cb2cb754cee87d7b6b4aa7502c3f1ef37ce
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add ARM PLL enablement

Add the low-level implementation to enable the ARM PLL oscillator, which
is disabled by default when booting the SoC. It will be used by PLL
diviers, for which

feat(nxp-clk): add ARM PLL enablement

Add the low-level implementation to enable the ARM PLL oscillator, which
is disabled by default when booting the SoC. It will be used by PLL
diviers, for which support will be added later.

Change-Id: I964fa7374ea9a08c695009176eade01003c1d6c2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for clock muxes

The clock muxes will simply pass the set rate request to the clock
module connected to its source, as they do not alter the frequency.

Change-Id: I5fda8fffa0

feat(nxp-clk): set rate for clock muxes

The clock muxes will simply pass the set rate request to the clock
module connected to its source, as they do not alter the frequency.

Change-Id: I5fda8fffa0f46a4be96deac4d6a5a880c9f86ccf
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for clock fixed divider

Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.

Change-Id: I8a29a2c5b1a829db0c39640

feat(nxp-clk): set rate for clock fixed divider

Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.

Change-Id: I8a29a2c5b1a829db0c396407c3517c9e66caaa93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add A53 clock objects

These objects are needed to allow early enablement of the A53 core
clock.

Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): add A53 clock objects

These objects are needed to allow early enablement of the A53 core
clock.

Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for PLL divider objects

Add implementation for ARM PLL divider rate set mechanism.

Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <g

feat(nxp-clk): set rate for PLL divider objects

Add implementation for ARM PLL divider rate set mechanism.

Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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