1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright 2020-2021, 2023-2024 NXP 4 */ 5 #ifndef S32CC_CLK_REGS_H 6 #define S32CC_CLK_REGS_H 7 8 #include <lib/utils_def.h> 9 10 #define FXOSC_BASE_ADDR (0x40050000UL) 11 #define ARMPLL_BASE_ADDR (0x40038000UL) 12 #define ARM_DFS_BASE_ADDR (0x40054000UL) 13 #define CGM1_BASE_ADDR (0x40034000UL) 14 15 /* FXOSC */ 16 #define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL) 17 #define FXOSC_CTRL_OSC_BYP BIT_32(31U) 18 #define FXOSC_CTRL_COMP_EN BIT_32(24U) 19 #define FXOSC_CTRL_EOCV_OFFSET 16U 20 #define FXOSC_CTRL_EOCV_MASK GENMASK_32(23U, FXOSC_CTRL_EOCV_OFFSET) 21 #define FXOSC_CTRL_EOCV(VAL) (FXOSC_CTRL_EOCV_MASK & \ 22 ((uint32_t)(VAL) << FXOSC_CTRL_EOCV_OFFSET)) 23 #define FXOSC_CTRL_GM_SEL_OFFSET 4U 24 #define FXOSC_CTRL_GM_SEL_MASK GENMASK_32(7U, FXOSC_CTRL_GM_SEL_OFFSET) 25 #define FXOSC_CTRL_GM_SEL(VAL) (FXOSC_CTRL_GM_SEL_MASK & \ 26 ((uint32_t)(VAL) << FXOSC_CTRL_GM_SEL_OFFSET)) 27 #define FXOSC_CTRL_OSCON BIT_32(0U) 28 29 #define FXOSC_STAT(FXOSC) ((FXOSC) + 0x4UL) 30 #define FXOSC_STAT_OSC_STAT BIT_32(31U) 31 32 /* PLL */ 33 #define PLLDIG_PLLCR(PLL) ((PLL) + 0x0UL) 34 #define PLLDIG_PLLCR_PLLPD BIT_32(31U) 35 36 #define PLLDIG_PLLSR(PLL) ((PLL) + 0x4UL) 37 #define PLLDIG_PLLSR_LOCK BIT_32(2U) 38 39 #define PLLDIG_PLLDV(PLL) ((PLL) + 0x8UL) 40 #define PLLDIG_PLLDV_RDIV_OFFSET 12U 41 #define PLLDIG_PLLDV_RDIV_MASK GENMASK_32(14U, PLLDIG_PLLDV_RDIV_OFFSET) 42 #define PLLDIG_PLLDV_RDIV_SET(VAL) (PLLDIG_PLLDV_RDIV_MASK & \ 43 ((VAL) << PLLDIG_PLLDV_RDIV_OFFSET)) 44 #define PLLDIG_PLLDV_MFI_MASK GENMASK_32(7U, 0U) 45 #define PLLDIG_PLLDV_MFI(DIV) (PLLDIG_PLLDV_MFI_MASK & (DIV)) 46 47 #define PLLDIG_PLLFD(PLL) ((PLL) + 0x10UL) 48 #define PLLDIG_PLLFD_SMDEN BIT_32(30U) 49 #define PLLDIG_PLLFD_MFN_MASK GENMASK_32(14U, 0U) 50 #define PLLDIG_PLLFD_MFN_SET(VAL) (PLLDIG_PLLFD_MFN_MASK & (VAL)) 51 52 #define PLLDIG_PLLCLKMUX(PLL) ((PLL) + 0x20UL) 53 54 #define PLLDIG_PLLODIV(PLL, N) ((PLL) + 0x80UL + ((N) * 0x4UL)) 55 #define PLLDIG_PLLODIV_DE BIT_32(31U) 56 #define PLLDIG_PLLODIV_DIV_OFFSET 16U 57 #define PLLDIG_PLLODIV_DIV_MASK GENMASK_32(23U, PLLDIG_PLLODIV_DIV_OFFSET) 58 #define PLLDIG_PLLODIV_DIV(VAL) (((VAL) & PLLDIG_PLLODIV_DIV_MASK) >> \ 59 PLLDIG_PLLODIV_DIV_OFFSET) 60 #define PLLDIG_PLLODIV_DIV_SET(VAL) (PLLDIG_PLLODIV_DIV_MASK & ((VAL) << \ 61 PLLDIG_PLLODIV_DIV_OFFSET)) 62 63 /* MMC_CGM */ 64 #define CGM_MUXn_CSC(CGM_ADDR, MUX) ((CGM_ADDR) + 0x300UL + ((MUX) * 0x40UL)) 65 #define MC_CGM_MUXn_CSC_SELCTL_OFFSET 24U 66 #define MC_CGM_MUXn_CSC_SELCTL_MASK GENMASK_32(29U, MC_CGM_MUXn_CSC_SELCTL_OFFSET) 67 #define MC_CGM_MUXn_CSC_SELCTL(val) (MC_CGM_MUXn_CSC_SELCTL_MASK & ((val) \ 68 << MC_CGM_MUXn_CSC_SELCTL_OFFSET)) 69 #define MC_CGM_MUXn_CSC_CLK_SW BIT_32(2U) 70 #define MC_CGM_MUXn_CSC_SAFE_SW BIT_32(3U) 71 72 #define CGM_MUXn_CSS(CGM_ADDR, MUX) ((CGM_ADDR) + 0x304UL + ((MUX) * 0x40UL)) 73 #define MC_CGM_MUXn_CSS_SELSTAT_OFFSET 24U 74 #define MC_CGM_MUXn_CSS_SELSTAT_MASK GENMASK_32(29U, MC_CGM_MUXn_CSS_SELSTAT_OFFSET) 75 #define MC_CGM_MUXn_CSS_SELSTAT(css) ((MC_CGM_MUXn_CSS_SELSTAT_MASK & (css))\ 76 >> MC_CGM_MUXn_CSS_SELSTAT_OFFSET) 77 #define MC_CGM_MUXn_CSS_SWTRG(css) ((MC_CGM_MUXn_CSS_SWTRG_MASK & (css)) \ 78 >> MC_CGM_MUXn_CSS_SWTRG_OFFSET) 79 #define MC_CGM_MUXn_CSS_SWTRG_OFFSET 17U 80 #define MC_CGM_MUXn_CSS_SWTRG_MASK GENMASK_32(19U, MC_CGM_MUXn_CSS_SWTRG_OFFSET) 81 #define MC_CGM_MUXn_CSS_SWTRG_SUCCESS 0x1U 82 #define MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK 0x4U 83 #define MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK_INACTIVE 0x5U 84 #define MC_CGM_MUXn_CSS_SWIP BIT_32(16U) 85 #define MC_CGM_MUXn_CSS_SAFE_SW BIT_32(3U) 86 87 /* DFS */ 88 #define DFS_PORTSR(DFS_ADDR) ((DFS_ADDR) + 0xCUL) 89 #define DFS_PORTOLSR(DFS_ADDR) ((DFS_ADDR) + 0x10UL) 90 #define DFS_PORTOLSR_LOL(N) (BIT_32(N) & GENMASK_32(5U, 0U)) 91 #define DFS_PORTRESET(DFS_ADDR) ((DFS_ADDR) + 0x14UL) 92 #define DFS_PORTRESET_MASK GENMASK_32(5U, 0U) 93 #define DFS_PORTRESET_SET(VAL) (((VAL) & DFS_PORTRESET_MASK)) 94 95 #define DFS_CTL(DFS_ADDR) ((DFS_ADDR) + 0x18UL) 96 #define DFS_CTL_RESET BIT_32(1U) 97 98 #define DFS_DVPORTn(DFS_ADDR, PORT) ((DFS_ADDR) + 0x1CUL + ((PORT) * 0x4UL)) 99 #define DFS_DVPORTn_MFI_MASK GENMASK_32(15U, 8U) 100 #define DFS_DVPORTn_MFI_SHIFT 8U 101 #define DFS_DVPORTn_MFN_MASK GENMASK_32(7U, 0U) 102 #define DFS_DVPORTn_MFN_SHIFT 0U 103 #define DFS_DVPORTn_MFI(MFI) (((MFI) & DFS_DVPORTn_MFI_MASK) >> DFS_DVPORTn_MFI_SHIFT) 104 #define DFS_DVPORTn_MFN(MFN) (((MFN) & DFS_DVPORTn_MFN_MASK) >> DFS_DVPORTn_MFN_SHIFT) 105 #define DFS_DVPORTn_MFI_SET(VAL) (((VAL) << DFS_DVPORTn_MFI_SHIFT) & DFS_DVPORTn_MFI_MASK) 106 #define DFS_DVPORTn_MFN_SET(VAL) (((VAL) << DFS_DVPORTn_MFN_SHIFT) & DFS_DVPORTn_MFN_MASK) 107 108 #endif /* S32CC_CLK_REGS_H */ 109