core: spmc: support virtualization with SPMC at S-EL1

Adds support for virtualization with OP-TEE as SPMC at S-EL1. This if
the FF-A counterpart of SMC based ABI with virtualization.

Reviewed-by: B

core: spmc: support virtualization with SPMC at S-EL1

Adds support for virtualization with OP-TEE as SPMC at S-EL1. This if
the FF-A counterpart of SMC based ABI with virtualization.

Reviewed-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: register spmc_init() with boot_final()

In case of virtualization registers spmc_init() with boot_final()
instead of service_init() to have my_endpoint_id initialized as part of
boot initializa

core: register spmc_init() with boot_final()

In case of virtualization registers spmc_init() with boot_final()
instead of service_init() to have my_endpoint_id initialized as part of
boot initialization instead of delayed initialization when the OP-TEE
partition is created.

This guarantees that my_endpoint_id holds the correct value when the
first FF-A request is received.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add virt_get_current_guest_id()

Adds the helper function virt_get_current_guest_id().

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander

core: add virt_get_current_guest_id()

Adds the helper function virt_get_current_guest_id().

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: support FF-A 1.1

Adds support for FF-A 1.1. Now OP-TEE will need to be able to work with
both version 1.0 and 1.1 depending on the other endpoint. The callee
supplies its implemented ver

core: spmc: support FF-A 1.1

Adds support for FF-A 1.1. Now OP-TEE will need to be able to work with
both version 1.0 and 1.1 depending on the other endpoint. The callee
supplies its implemented version and OP-TEE chooses the highest common
version and returns that. This is done per endpoint so some endpoint may
very well use version 1.0 while another uses version 1.1.

Two data structures, struct ffa_mem_transaction and struct
ffa_partition_info, are affected. Runtime conditionals are used to
select which version to use based on the negotiated FF-A version.

Reviewed-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: improve checks in handle_mem_share()

For the two FF-A functions FFA_MEM_SHARE_64 and FFA_MEM_SHARE_32 update
the checks in handle_mem_share() for:
- 32-bit vs 64-bit calling convention,

core: spmc: improve checks in handle_mem_share()

For the two FF-A functions FFA_MEM_SHARE_64 and FFA_MEM_SHARE_32 update
the checks in handle_mem_share() for:
- 32-bit vs 64-bit calling convention, that is, when to mask of the
upper 32 bits.
- that the reported fragment length does not exceed the total length of
the memory transaction descriptor.

Reviewed-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: use adr_l for __nex_bss_start and __nex_bss_end

Fixes the following linker errors when CFG_NS_VIRTUALIZATION is enabled:
.../entry_a64.o: in function `clear_bss':
.../entry_a64.

core: arm64: use adr_l for __nex_bss_start and __nex_bss_end

Fixes the following linker errors when CFG_NS_VIRTUALIZATION is enabled:
.../entry_a64.o: in function `clear_bss':
.../entry_a64.S:237:(.text._start+0x8c): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__nex_bss_start' defined in .bss.mempool_default section in all_objs.o
.../entry_a64.S:238:(.text._start+0x90): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__nex_bss_end' defined in .bss.mempool_default section in all_objs.o

Use the adr_l macro instead of adr to get the addresses for start and
end of .nex_bss.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: plat-virt: Override default platform ISA extensions

RV64 virtual platform on QEMU supports C(compressed), Zicsr, and
Zifencei extensions. To specify the ISA extensions into RISC-V
toolchain s

riscv: plat-virt: Override default platform ISA extensions

RV64 virtual platform on QEMU supports C(compressed), Zicsr, and
Zifencei extensions. To specify the ISA extensions into RISC-V
toolchain so that toolchain can generate the code correctly, these
ISA extensions should be encoded into "-march" flag. This patch
overrides the default ISA extensions which is defined in riscv.mk
to specify the extension that the platform really supports.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Add default variables for platform ISA, ABI and code model

In RISC-V, each platform may have different supported ISA extensions,
ABI, and code model. In this commit, we define the defau

core: riscv: Add default variables for platform ISA, ABI and code model

In RISC-V, each platform may have different supported ISA extensions,
ABI, and code model. In this commit, we define the default variables
of ISA extensions, ABI, and code model in RISC-V core Makefile. The
platform can further overrides the values in their plat-*/conf.mk.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: interrupt: rename itr_init()

Renames itr_init() to interrupt_main_init() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <je

core: interrupt: rename itr_init()

Renames itr_init() to interrupt_main_init() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: interrupt: rename itr_core_handler()

Renames itr_core_handler() to interrupt_main_handler() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by:

core: interrupt: rename itr_core_handler()

Renames itr_core_handler() to interrupt_main_handler() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: gic: factorize call to gic_init() or gic_init_base_addr()

Platforms call either gic_init() or gic_init_base_addr() depending
on whether CFG_WITH_ARM_TRUSTED_FW is defined or not. This chang

drivers: gic: factorize call to gic_init() or gic_init_base_addr()

Platforms call either gic_init() or gic_init_base_addr() depending
on whether CFG_WITH_ARM_TRUSTED_FW is defined or not. This change
factorize this logic from gic_init() implementation and makes
gic_init_base_addr() local to gic.c.

For that purpose functions gic_init_base_address() and gic_dt_get_irq()
are moved inside gic.c source file.
source file.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: define main interrupt controller data from its driver

All but one platforms define CPU core interrupt controller from their
platform main.c source file next to its main interrupt handler.
This

core: define main interrupt controller data from its driver

All but one platforms define CPU core interrupt controller from their
platform main.c source file next to its main interrupt handler.
This change factorize these implementation by moving the definition
of the controller data instance straight in the controller driver
source file. This change makes each controller driver to implement
straight itr_core_handler() function, preventing a extra branch on
interrupt execution. Interrupt controller driver initialization
function now straight calls itr_core_init().

This changes treats case when CFG_CORE_WORKAROUND_ARM_NMFI is enable
to not conflict with core/arch/arm/kernel/thread.c that already
overrides itr_core_handler() weak implementation.

With this change, the main controller initialization function
(gic_init(), gic_init_base_addr(), gic_cpu_init() and hfic_init())
no more gets the controller data as input argument.

As a consequence, definition of struct hfic_data and struct gic_data
moves from their respective driver header file to the respective
driver source file.

As a consequence, gic_dump() no more requires an argument.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-sam: enable pinctrl and atmel_pio driver for wlsom1 board

The board will need these options to apply I2C pin muxing in order to
communicate with the PMIC.

Signed-off-by: Clément Léger <clement

plat-sam: enable pinctrl and atmel_pio driver for wlsom1 board

The board will need these options to apply I2C pin muxing in order to
communicate with the PMIC.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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dts: at91: set PIO controller as secure

Set the PIO pinctrl as secure to ensure pin configurations are not
modifiable by non secure world.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
A

dts: at91: set PIO controller as secure

Set the PIO pinctrl as secure to ensure pin configurations are not
modifiable by non secure world.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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plat-sam: enable CFG_DRIVERS_GPIO for sama5d27_wlsom1_ek flavor

The PMIC present on this board will needs to access a GPIOs to enter low
power mode.

Signed-off-by: Clément Léger <clement.leger@boot

plat-sam: enable CFG_DRIVERS_GPIO for sama5d27_wlsom1_ek flavor

The PMIC present on this board will needs to access a GPIOs to enter low
power mode.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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dt_driver_test: add tests for gpio controller framework

Add various tests for the GPIO dt controller framework much like what was
done for the rstclr system.

Signed-off-by: Clément Léger <clement.l

dt_driver_test: add tests for gpio controller framework

Add various tests for the GPIO dt controller framework much like what was
done for the rstclr system.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-sam: registers clocks for SCMI usage

Use scmi_clk_add() to register all clocks that are available on the
sama5d2 SoC.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne

plat-sam: registers clocks for SCMI usage

Use scmi_clk_add() to register all clocks that are available on the
sama5d2 SoC.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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plat-sam: enable use of SCMI generic clock support

All clocks for the plat-sam are described using the clk framework.
Enable this option to allow using them with SCMI transparently.

Signed-off-by:

plat-sam: enable use of SCMI generic clock support

All clocks for the plat-sam are described using the clk framework.
Enable this option to allow using them with SCMI transparently.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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plat-sam: add support for CFG_SCMI_MSG_SMT_FASTCALL_ENTRY

Add necessary calls to scmi_smt_fastcall_smc_entry from sm_platform
handler to be able to do SCMI calls via SMC.

Signed-off-by: Clément Lég

plat-sam: add support for CFG_SCMI_MSG_SMT_FASTCALL_ENTRY

Add necessary calls to scmi_smt_fastcall_smc_entry from sm_platform
handler to be able to do SCMI calls via SMC.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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plat-sam: add SCMI server foundation

Add foundations for SCMI server support. This will be used to expose
clocks and regulators to non-secure world.

Signed-off-by: Clément Léger <clement.leger@boot

plat-sam: add SCMI server foundation

Add foundations for SCMI server support. This will be used to expose
clocks and regulators to non-secure world.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

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plat-sam: nsec-service: Fix include order

Reorder includes in alphabetical order.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

plat-rzn1: increase DDR size to 1GB

There are now some RZ/N1 devices with 1GB rather than 256MB. The
first-stage bootloader does not support passing a DT to OP-TEE, so
static values are set at compi

plat-rzn1: increase DDR size to 1GB

There are now some RZ/N1 devices with 1GB rather than 256MB. The
first-stage bootloader does not support passing a DT to OP-TEE, so
static values are set at compile time. Increase the DDR size so as to
avoid OP-TEE calls failing with TEEC_ERROR_OUT_OF_MEMORY.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

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core: riscv: kernel: Add missing initialization for core local stacks

The thread core local stacks should be initialized when the primary core
performs system initialization.

Fixes: ca8258906949 ("

core: riscv: kernel: Add missing initialization for core local stacks

The thread core local stacks should be initialized when the primary core
performs system initialization.

Fixes: ca8258906949 ("core: split core/arch/arm/kernel/thread.c")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: support physically relocatable OP-TEE binary

With CFG_CORE_PHYS_RELOCATABLE=y enable support in OP-TEE to relocate
itself to allow it to run from physical address that differs from the
link ad

core: support physically relocatable OP-TEE binary

With CFG_CORE_PHYS_RELOCATABLE=y enable support in OP-TEE to relocate
itself to allow it to run from physical address that differs from the
link address.

This feature is currently only supported with CFG_CORE_SEL2_SPMC=y since
the TEE core has to know the range of available memory. With SPMC at EL2
this is accomplished via get_sec_mem_from_manifest(). An SPMC at S-EL2
may need to load OP-TEE at a different address depending on
configuration.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: parse boot info

With CFG_CORE_SEL2_SPMC=y OP-TEE is executed as an SP at S-EL1. The
manifest describing the OP-TEE SP is passed as a boot argument.

The manifest contains among other thin

core: ffa: parse boot info

With CFG_CORE_SEL2_SPMC=y OP-TEE is executed as an SP at S-EL1. The
manifest describing the OP-TEE SP is passed as a boot argument.

The manifest contains among other things the two properties
"load-address" and "mem-size". These cover the secure memory allocated
for OP-TEE to cover core and TA memory. The retrieved memory range is
saved with a call to core_mmu_set_secure_memory() to be used when
initializing MMU and other memory configuration.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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