1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2015-2022, Linaro Limited 4 * Copyright (c) 2021-2023, Arm Limited 5 */ 6 7#include <platform_config.h> 8 9#include <arm64_macros.S> 10#include <arm.h> 11#include <asm.S> 12#include <generated/asm-defines.h> 13#include <keep.h> 14#include <kernel/thread_private.h> 15#include <mm/core_mmu.h> 16#include <sm/optee_smc.h> 17#include <sm/teesmc_opteed.h> 18#include <sm/teesmc_opteed_macros.h> 19 20 /* 21 * Setup SP_EL0 and SPEL1, SP will be set to SP_EL0. 22 * SP_EL0 is assigned: 23 * stack_tmp + (cpu_id + 1) * stack_tmp_stride - STACK_TMP_GUARD 24 * SP_EL1 is assigned thread_core_local[cpu_id] 25 */ 26 .macro set_sp 27 bl __get_core_pos 28 cmp x0, #CFG_TEE_CORE_NB_CORE 29 /* Unsupported CPU, park it before it breaks something */ 30 bge unhandled_cpu 31 add x0, x0, #1 32 adr_l x1, stack_tmp_stride 33 ldr w1, [x1] 34 mul x1, x0, x1 35 36 /* x0 = stack_tmp - STACK_TMP_GUARD */ 37 adr_l x2, stack_tmp_rel 38 ldr w0, [x2] 39 add x0, x0, x2 40 41 msr spsel, #0 42 add sp, x1, x0 43 bl thread_get_core_local 44 msr spsel, #1 45 mov sp, x0 46 msr spsel, #0 47 .endm 48 49 .macro read_feat_mte reg 50 mrs \reg, id_aa64pfr1_el1 51 ubfx \reg, \reg, #ID_AA64PFR1_EL1_MTE_SHIFT, #4 52 .endm 53 54 .macro set_sctlr_el1 55 mrs x0, sctlr_el1 56 orr x0, x0, #SCTLR_I 57 orr x0, x0, #SCTLR_SA 58 orr x0, x0, #SCTLR_SPAN 59#if defined(CFG_CORE_RWDATA_NOEXEC) 60 orr x0, x0, #SCTLR_WXN 61#endif 62#if defined(CFG_SCTLR_ALIGNMENT_CHECK) 63 orr x0, x0, #SCTLR_A 64#else 65 bic x0, x0, #SCTLR_A 66#endif 67#ifdef CFG_MEMTAG 68 read_feat_mte x1 69 cmp w1, #1 70 b.ls 111f 71 orr x0, x0, #(SCTLR_ATA | SCTLR_ATA0) 72 bic x0, x0, #SCTLR_TCF_MASK 73 bic x0, x0, #SCTLR_TCF0_MASK 74111: 75#endif 76#if defined(CFG_TA_PAUTH) && defined(CFG_TA_BTI) 77 orr x0, x0, #SCTLR_BT0 78#endif 79#if defined(CFG_CORE_PAUTH) && defined(CFG_CORE_BTI) 80 orr x0, x0, #SCTLR_BT1 81#endif 82 msr sctlr_el1, x0 83 .endm 84 85 .macro init_memtag_per_cpu 86 read_feat_mte x0 87 cmp w0, #1 88 b.ls 11f 89 90#ifdef CFG_TEE_CORE_DEBUG 91 /* 92 * This together with GCR_EL1.RRND = 0 will make the tags 93 * acquired with the irg instruction deterministic. 94 */ 95 mov_imm x0, 0xcafe00 96 msr rgsr_el1, x0 97 /* Avoid tag = 0x0 and 0xf */ 98 mov x0, #0 99#else 100 /* 101 * Still avoid tag = 0x0 and 0xf as we use that tag for 102 * everything which isn't explicitly tagged. Setting 103 * GCR_EL1.RRND = 1 to allow an implementation specific 104 * method of generating the tags. 105 */ 106 mov x0, #GCR_EL1_RRND 107#endif 108 orr x0, x0, #1 109 orr x0, x0, #(1 << 15) 110 msr gcr_el1, x0 111 112 /* 113 * Enable the tag checks on the current CPU. 114 * 115 * Depends on boot_init_memtag() having cleared tags for 116 * TEE core memory. Well, not really, addresses with the 117 * tag value 0b0000 will use unchecked access due to 118 * TCR_TCMA0. 119 */ 120 mrs x0, tcr_el1 121 orr x0, x0, #TCR_TBI0 122 orr x0, x0, #TCR_TCMA0 123 msr tcr_el1, x0 124 125 mrs x0, sctlr_el1 126 orr x0, x0, #SCTLR_TCF_SYNC 127 orr x0, x0, #SCTLR_TCF0_SYNC 128 msr sctlr_el1, x0 129 130 isb 13111: 132 .endm 133 134 .macro init_pauth_per_cpu 135 msr spsel, #1 136 ldp x0, x1, [sp, #THREAD_CORE_LOCAL_KEYS] 137 msr spsel, #0 138 write_apiakeyhi x0 139 write_apiakeylo x1 140 mrs x0, sctlr_el1 141 orr x0, x0, #SCTLR_ENIA 142 msr sctlr_el1, x0 143 isb 144 .endm 145 146FUNC _start , : 147 /* 148 * Register use: 149 * x0 - CFG_CORE_FFA=y && CFG_CORE_SEL2_SPMC=n: 150 * if non-NULL holds the TOS FW config [1] address 151 * - CFG_CORE_FFA=y && CFG_CORE_SEL2_SPMC=y: 152 * address of FF-A Boot Information Blob 153 * - CFG_CORE_FFA=n: 154 * if non-NULL holds the pagable part address 155 * x2 - CFG_CORE_SEL2_SPMC=n: 156 * if non-NULL holds the system DTB address 157 * 158 * x19 - saved x0 159 * x20 - saved x2 160 * 161 * [1] A TF-A concept: TOS_FW_CONFIG - Trusted OS Firmware 162 * configuration file. Used by Trusted OS (BL32), that is, OP-TEE 163 * here. 164 */ 165 mov x19, x0 166#if defined(CFG_DT_ADDR) 167 ldr x20, =CFG_DT_ADDR 168#else 169 mov x20, x2 /* Save DT address */ 170#endif 171 172 adr x0, reset_vect_table 173 msr vbar_el1, x0 174 isb 175 176 set_sctlr_el1 177 isb 178 179#ifdef CFG_WITH_PAGER 180 /* 181 * Move init code into correct location and move hashes to a 182 * temporary safe location until the heap is initialized. 183 * 184 * The binary is built as: 185 * [Pager code, rodata and data] : In correct location 186 * [Init code and rodata] : Should be copied to __init_start 187 * [struct boot_embdata + data] : Should be saved before 188 * initializing pager, first uint32_t tells the length of the data 189 */ 190 adr x0, __init_start /* dst */ 191 adr x1, __data_end /* src */ 192 adr x2, __init_end 193 sub x2, x2, x0 /* init len */ 194 ldr w4, [x1, x2] /* length of hashes etc */ 195 add x2, x2, x4 /* length of init and hashes etc */ 196 /* Copy backwards (as memmove) in case we're overlapping */ 197 add x0, x0, x2 /* __init_start + len */ 198 add x1, x1, x2 /* __data_end + len */ 199 adr x3, cached_mem_end 200 str x0, [x3] 201 adr x2, __init_start 202copy_init: 203 ldp x3, x4, [x1, #-16]! 204 stp x3, x4, [x0, #-16]! 205 cmp x0, x2 206 b.gt copy_init 207#else 208 /* 209 * The binary is built as: 210 * [Core, rodata and data] : In correct location 211 * [struct boot_embdata + data] : Should be moved to __end, first 212 * uint32_t tells the length of the struct + data 213 */ 214 adr_l x0, __end /* dst */ 215 adr_l x1, __data_end /* src */ 216 ldr w2, [x1] /* struct boot_embdata::total_len */ 217 /* Copy backwards (as memmove) in case we're overlapping */ 218 add x0, x0, x2 219 add x1, x1, x2 220 adr x3, cached_mem_end 221 str x0, [x3] 222 adr_l x2, __end 223 224copy_init: 225 ldp x3, x4, [x1, #-16]! 226 stp x3, x4, [x0, #-16]! 227 cmp x0, x2 228 b.gt copy_init 229#endif 230 231 /* 232 * Clear .bss, this code obviously depends on the linker keeping 233 * start/end of .bss at least 8 byte aligned. 234 */ 235 adr_l x0, __bss_start 236 adr_l x1, __bss_end 237clear_bss: 238 str xzr, [x0], #8 239 cmp x0, x1 240 b.lt clear_bss 241 242#ifdef CFG_NS_VIRTUALIZATION 243 /* 244 * Clear .nex_bss, this code obviously depends on the linker keeping 245 * start/end of .bss at least 8 byte aligned. 246 */ 247 adr x0, __nex_bss_start 248 adr x1, __nex_bss_end 249clear_nex_bss: 250 str xzr, [x0], #8 251 cmp x0, x1 252 b.lt clear_nex_bss 253#endif 254 255 /* Setup SP_EL0 and SP_EL1, SP will be set to SP_EL0 */ 256 set_sp 257 258 bl thread_init_thread_core_local 259 260 /* Enable aborts now that we can receive exceptions */ 261 msr daifclr, #DAIFBIT_ABT 262 263 /* 264 * Invalidate dcache for all memory used during initialization to 265 * avoid nasty surprices when the cache is turned on. We must not 266 * invalidate memory not used by OP-TEE since we may invalidate 267 * entries used by for instance ARM Trusted Firmware. 268 */ 269 adr_l x0, __text_start 270 ldr x1, cached_mem_end 271 sub x1, x1, x0 272 bl dcache_cleaninv_range 273 274 /* Enable Console */ 275 bl console_init 276 277#if defined(CFG_CORE_SEL2_SPMC) && defined(CFG_CORE_PHYS_RELOCATABLE) 278 mov x0, x19 /* boot info */ 279 bl boot_save_boot_info 280#endif 281 282#ifdef CFG_MEMTAG 283 /* 284 * If FEAT_MTE2 is available, initializes the memtag callbacks. 285 * Tags for OP-TEE core memory are then cleared to make it safe to 286 * enable MEMTAG below. 287 */ 288 bl boot_init_memtag 289#endif 290 291#ifdef CFG_CORE_ASLR 292 mov x0, x20 /* DT address */ 293 bl get_aslr_seed 294#else 295 mov x0, #0 296#endif 297 298 adr x1, boot_mmu_config 299 bl core_init_mmu_map 300 301#ifdef CFG_CORE_ASLR 302 /* 303 * Process relocation information again updating for the virtual 304 * map offset. We're doing this now before MMU is enabled as some 305 * of the memory will become write protected. 306 */ 307 ldr x0, boot_mmu_config + CORE_MMU_CONFIG_MAP_OFFSET 308 /* 309 * Update cached_mem_end address with load offset since it was 310 * calculated before relocation. 311 */ 312 adr x5, cached_mem_end 313 ldr x6, [x5] 314 add x6, x6, x0 315 str x6, [x5] 316 bl relocate 317#endif 318 319 bl __get_core_pos 320 bl enable_mmu 321#ifdef CFG_CORE_ASLR 322 /* 323 * Reinitialize console, since register_serial_console() has 324 * previously registered a PA and with ASLR the VA is different 325 * from the PA. 326 */ 327 bl console_init 328#endif 329 330#ifdef CFG_NS_VIRTUALIZATION 331 /* 332 * Initialize partition tables for each partition to 333 * default_partition which has been relocated now to a different VA 334 */ 335 bl core_mmu_set_default_prtn_tbl 336#endif 337 338#ifdef CFG_CORE_SEL1_SPMC 339 mov x0, xzr /* pager not used */ 340#else 341 mov x0, x19 /* pagable part address */ 342#endif 343 mov x1, #-1 344 bl boot_init_primary_early 345 346#ifdef CFG_MEMTAG 347 init_memtag_per_cpu 348#endif 349 350#ifndef CFG_NS_VIRTUALIZATION 351 mov x21, sp 352 adr_l x0, threads 353 ldr x0, [x0, #THREAD_CTX_STACK_VA_END] 354 mov sp, x0 355 bl thread_get_core_local 356 mov x22, x0 357 str wzr, [x22, #THREAD_CORE_LOCAL_FLAGS] 358#endif 359 mov x0, x20 /* DT address also known as HW_CONFIG */ 360#ifdef CFG_CORE_SEL1_SPMC 361 mov x1, x19 /* TOS_FW_CONFIG DT address */ 362#else 363 mov x1, xzr /* unused */ 364#endif 365 bl boot_init_primary_late 366#ifdef CFG_CORE_PAUTH 367 init_pauth_per_cpu 368#endif 369 370#ifndef CFG_NS_VIRTUALIZATION 371 mov x0, #THREAD_CLF_TMP 372 str w0, [x22, #THREAD_CORE_LOCAL_FLAGS] 373 mov sp, x21 374#endif 375 376#ifdef _CFG_CORE_STACK_PROTECTOR 377 /* Update stack canary value */ 378 bl plat_get_random_stack_canary 379 adr_l x5, __stack_chk_guard 380 str x0, [x5] 381#endif 382 383 /* 384 * In case we've touched memory that secondary CPUs will use before 385 * they have turned on their D-cache, clean and invalidate the 386 * D-cache before exiting to normal world. 387 */ 388 adr_l x0, __text_start 389 ldr x1, cached_mem_end 390 sub x1, x1, x0 391 bl dcache_cleaninv_range 392 393 394 /* 395 * Clear current thread id now to allow the thread to be reused on 396 * next entry. Matches the thread_init_boot_thread in 397 * boot.c. 398 */ 399#ifndef CFG_NS_VIRTUALIZATION 400 bl thread_clr_boot_thread 401#endif 402 403#ifdef CFG_CORE_FFA 404 adr x0, cpu_on_handler 405 /* 406 * Compensate for the virtual map offset since cpu_on_handler() is 407 * called with MMU off. 408 */ 409 ldr x1, boot_mmu_config + CORE_MMU_CONFIG_MAP_OFFSET 410 sub x0, x0, x1 411 bl thread_spmc_register_secondary_ep 412 b thread_ffa_msg_wait 413#else 414 /* 415 * Pass the vector address returned from main_init Compensate for 416 * the virtual map offset since cpu_on_handler() is called with MMU 417 * off. 418 */ 419 ldr x0, boot_mmu_config + CORE_MMU_CONFIG_MAP_OFFSET 420 adr x1, thread_vector_table 421 sub x1, x1, x0 422 mov x0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 423 smc #0 424 /* SMC should not return */ 425 panic_at_smc_return 426#endif 427END_FUNC _start 428DECLARE_KEEP_INIT _start 429 430 .section .identity_map.data 431 .balign 8 432LOCAL_DATA cached_mem_end , : 433 .skip 8 434END_DATA cached_mem_end 435 436#ifdef CFG_CORE_ASLR 437LOCAL_FUNC relocate , : 438 /* x0 holds load offset */ 439#ifdef CFG_WITH_PAGER 440 adr_l x6, __init_end 441#else 442 adr_l x6, __end 443#endif 444 ldp w2, w3, [x6, #BOOT_EMBDATA_RELOC_OFFSET] 445 446 mov_imm x1, TEE_LOAD_ADDR 447 add x2, x2, x6 /* start of relocations */ 448 add x3, x3, x2 /* end of relocations */ 449 450 /* 451 * Relocations are not formatted as Rela64, instead they are in a 452 * compressed format created by get_reloc_bin() in 453 * scripts/gen_tee_bin.py 454 * 455 * All the R_AARCH64_RELATIVE relocations are translated into a 456 * list of 32-bit offsets from TEE_LOAD_ADDR. At each address a 457 * 64-bit value pointed out which increased with the load offset. 458 */ 459 460#ifdef CFG_WITH_PAGER 461 /* 462 * With pager enabled we can only relocate the pager and init 463 * parts, the rest has to be done when a page is populated. 464 */ 465 sub x6, x6, x1 466#endif 467 468 b 2f 469 /* Loop over the relocation addresses and process all entries */ 4701: ldr w4, [x2], #4 471#ifdef CFG_WITH_PAGER 472 /* Skip too large addresses */ 473 cmp x4, x6 474 b.ge 2f 475#endif 476 add x4, x4, x1 477 ldr x5, [x4] 478 add x5, x5, x0 479 str x5, [x4] 480 4812: cmp x2, x3 482 b.ne 1b 483 484 ret 485END_FUNC relocate 486#endif 487 488/* 489 * void enable_mmu(unsigned long core_pos); 490 * 491 * This function depends on being mapped with in the identity map where 492 * physical address and virtual address is the same. After MMU has been 493 * enabled the instruction pointer will be updated to execute as the new 494 * offset instead. Stack pointers and the return address are updated. 495 */ 496LOCAL_FUNC enable_mmu , : , .identity_map 497 adr x1, boot_mmu_config 498 load_xregs x1, 0, 2, 6 499 /* 500 * x0 = core_pos 501 * x2 = tcr_el1 502 * x3 = mair_el1 503 * x4 = ttbr0_el1_base 504 * x5 = ttbr0_core_offset 505 * x6 = load_offset 506 */ 507 msr tcr_el1, x2 508 msr mair_el1, x3 509 510 /* 511 * ttbr0_el1 = ttbr0_el1_base + ttbr0_core_offset * core_pos 512 */ 513 madd x1, x5, x0, x4 514 msr ttbr0_el1, x1 515 msr ttbr1_el1, xzr 516 isb 517 518 /* Invalidate TLB */ 519 tlbi vmalle1 520 521 /* 522 * Make sure translation table writes have drained into memory and 523 * the TLB invalidation is complete. 524 */ 525 dsb sy 526 isb 527 528 /* Enable the MMU */ 529 mrs x1, sctlr_el1 530 orr x1, x1, #SCTLR_M 531 msr sctlr_el1, x1 532 isb 533 534 /* Update vbar */ 535 mrs x1, vbar_el1 536 add x1, x1, x6 537 msr vbar_el1, x1 538 isb 539 540 /* Invalidate instruction cache and branch predictor */ 541 ic iallu 542 isb 543 544 /* Enable I and D cache */ 545 mrs x1, sctlr_el1 546 orr x1, x1, #SCTLR_I 547 orr x1, x1, #SCTLR_C 548 msr sctlr_el1, x1 549 isb 550 551 /* Adjust stack pointers and return address */ 552 msr spsel, #1 553 add sp, sp, x6 554 msr spsel, #0 555 add sp, sp, x6 556 add x30, x30, x6 557 558 ret 559END_FUNC enable_mmu 560 561 .section .identity_map.data 562 .balign 8 563DATA boot_mmu_config , : /* struct core_mmu_config */ 564 .skip CORE_MMU_CONFIG_SIZE 565END_DATA boot_mmu_config 566 567FUNC cpu_on_handler , : 568 mov x19, x0 569 mov x20, x1 570 mov x21, x30 571 572 adr x0, reset_vect_table 573 msr vbar_el1, x0 574 isb 575 576 set_sctlr_el1 577 isb 578 579 /* Enable aborts now that we can receive exceptions */ 580 msr daifclr, #DAIFBIT_ABT 581 582 bl __get_core_pos 583 bl enable_mmu 584 585 /* Setup SP_EL0 and SP_EL1, SP will be set to SP_EL0 */ 586 set_sp 587 588#ifdef CFG_MEMTAG 589 init_memtag_per_cpu 590#endif 591#ifdef CFG_CORE_PAUTH 592 init_pauth_per_cpu 593#endif 594 595 mov x0, x19 596 mov x1, x20 597#ifdef CFG_CORE_FFA 598 bl boot_cpu_on_handler 599 b thread_ffa_msg_wait 600#else 601 mov x30, x21 602 b boot_cpu_on_handler 603#endif 604END_FUNC cpu_on_handler 605DECLARE_KEEP_PAGER cpu_on_handler 606 607LOCAL_FUNC unhandled_cpu , : 608 wfi 609 b unhandled_cpu 610END_FUNC unhandled_cpu 611 612LOCAL_DATA stack_tmp_rel , : 613 .word stack_tmp - stack_tmp_rel - STACK_TMP_GUARD 614END_DATA stack_tmp_rel 615 616 /* 617 * This macro verifies that the a given vector doesn't exceed the 618 * architectural limit of 32 instructions. This is meant to be placed 619 * immedately after the last instruction in the vector. It takes the 620 * vector entry as the parameter 621 */ 622 .macro check_vector_size since 623 .if (. - \since) > (32 * 4) 624 .error "Vector exceeds 32 instructions" 625 .endif 626 .endm 627 628 .section .identity_map, "ax", %progbits 629 .align 11 630LOCAL_FUNC reset_vect_table , :, .identity_map, , nobti 631 /* ----------------------------------------------------- 632 * Current EL with SP0 : 0x0 - 0x180 633 * ----------------------------------------------------- 634 */ 635SynchronousExceptionSP0: 636 b SynchronousExceptionSP0 637 check_vector_size SynchronousExceptionSP0 638 639 .align 7 640IrqSP0: 641 b IrqSP0 642 check_vector_size IrqSP0 643 644 .align 7 645FiqSP0: 646 b FiqSP0 647 check_vector_size FiqSP0 648 649 .align 7 650SErrorSP0: 651 b SErrorSP0 652 check_vector_size SErrorSP0 653 654 /* ----------------------------------------------------- 655 * Current EL with SPx: 0x200 - 0x380 656 * ----------------------------------------------------- 657 */ 658 .align 7 659SynchronousExceptionSPx: 660 b SynchronousExceptionSPx 661 check_vector_size SynchronousExceptionSPx 662 663 .align 7 664IrqSPx: 665 b IrqSPx 666 check_vector_size IrqSPx 667 668 .align 7 669FiqSPx: 670 b FiqSPx 671 check_vector_size FiqSPx 672 673 .align 7 674SErrorSPx: 675 b SErrorSPx 676 check_vector_size SErrorSPx 677 678 /* ----------------------------------------------------- 679 * Lower EL using AArch64 : 0x400 - 0x580 680 * ----------------------------------------------------- 681 */ 682 .align 7 683SynchronousExceptionA64: 684 b SynchronousExceptionA64 685 check_vector_size SynchronousExceptionA64 686 687 .align 7 688IrqA64: 689 b IrqA64 690 check_vector_size IrqA64 691 692 .align 7 693FiqA64: 694 b FiqA64 695 check_vector_size FiqA64 696 697 .align 7 698SErrorA64: 699 b SErrorA64 700 check_vector_size SErrorA64 701 702 /* ----------------------------------------------------- 703 * Lower EL using AArch32 : 0x0 - 0x180 704 * ----------------------------------------------------- 705 */ 706 .align 7 707SynchronousExceptionA32: 708 b SynchronousExceptionA32 709 check_vector_size SynchronousExceptionA32 710 711 .align 7 712IrqA32: 713 b IrqA32 714 check_vector_size IrqA32 715 716 .align 7 717FiqA32: 718 b FiqA32 719 check_vector_size FiqA32 720 721 .align 7 722SErrorA32: 723 b SErrorA32 724 check_vector_size SErrorA32 725 726END_FUNC reset_vect_table 727 728BTI(emit_aarch64_feature_1_and GNU_PROPERTY_AARCH64_FEATURE_1_BTI) 729