core: riscv: core_mmu_arch: zero-initialize new page tables

New page table pages must always start cleared. On some
platforms (e.g., QEMU) RAM happens to be zeroed at reset,
but on real hardware (FP

core: riscv: core_mmu_arch: zero-initialize new page tables

New page table pages must always start cleared. On some
platforms (e.g., QEMU) RAM happens to be zeroed at reset,
but on real hardware (FPGA/SoC DDR) may not be the case.
Without this memset, stale contents can make
core_mmu_map_region() see non-zero old_attr and panic with
"Page is already mapped" when CFG_DYN_CONFIG is enabled.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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crypto: asu: Add crypto hash driver

Add support for following Hash algorithms
SHA-256, SHA-384, SHA-512, SHA3-256, SHA3-384, SHA3-512

Signed-off-by: Harsh Jain <h.jain@amd.com>
Signed-off-by: Aksha

crypto: asu: Add crypto hash driver

Add support for following Hash algorithms
SHA-256, SHA-384, SHA-512, SHA3-256, SHA3-384, SHA3-512

Signed-off-by: Harsh Jain <h.jain@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: amd: Add ASU support

Add support for the AMD Application Security Unit (ASU), the on-chip
Hardware Security Module (HSM) for Versal Gen 2.
The ASU manages all device-level security services

drivers: amd: Add ASU support

Add support for the AMD Application Security Unit (ASU), the on-chip
Hardware Security Module (HSM) for Versal Gen 2.
The ASU manages all device-level security services for user
applications, extending beyond accelerator-centric tasks.
Its firmware also exposes several software-based cryptographic
primitives, including:
- Key transfer
- RSA authentication (multiple padding schemes)
- HMAC
- Key Derivation Function (KDF)
- Key wrap / unwrap

Co-developed-by: Harsh Jain <h.jain@amd.com>
Signed-off-by: Harsh Jain <h.jain@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Increase mailbox timeout to 1000ms

Mailbox driver waits for 10ms to get a response from TIFS, before
flagging the transaction a failure. 10ms seems to be right at the edge,
since u

plat-k3: drivers: Increase mailbox timeout to 1000ms

Mailbox driver waits for 10ms to get a response from TIFS, before
flagging the transaction a failure. 10ms seems to be right at the edge,
since unrelated updates to other components in the boot chain are
causing the actual wait time to increase. Therefore increase the timeout
to 1000ms.

1000ms is chosen to keep uniformity with the mailbox driver in TF-A.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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plat-rockchip: px30: set CFG_CRYPTO_WITH_CE ?= y

Similarly to what's been done to RK3399 in commit 3ab148c8f4a0
("plat-rockchip: rk3399: set CFG_CRYPTO_WITH_CE ?= y"), we can enable
the Arm Cryptogr

plat-rockchip: px30: set CFG_CRYPTO_WITH_CE ?= y

Similarly to what's been done to RK3399 in commit 3ab148c8f4a0
("plat-rockchip: rk3399: set CFG_CRYPTO_WITH_CE ?= y"), we can enable
the Arm Cryptography Extensions by default for PX30 as Rockchip claims
they are supported in the datasheet[1].

Tested with:

xtest --aes-perf -m XTS -s 1000000 -n 1000

Before:
min=88574.2us max=91273us mean=88942.8us stddev=234.498us (cv 0.26365%) (10.7223MiB/s)

After:
min=3297.58us max=3655.75us mean=3464.66us stddev=59.7159us (cv 1.72357%) (275.258MiB/s)

Link: https://opensource.rock-chips.com/images/8/87/Rockchip_PX30_Datasheet_V1.4-20191227.pdf [1]
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>

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core: arm: link.mk: Fix typo for python command line

Fix typo for python command line
$(q)scripts/gen_tee_bin.py => $(q)$(PYTHON3) scripts/gen_tee_bin.py

Signed-off-by: guan-gm.lin <guan-gm.lin@med

core: arm: link.mk: Fix typo for python command line

Fix typo for python command line
$(q)scripts/gen_tee_bin.py => $(q)$(PYTHON3) scripts/gen_tee_bin.py

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-rockchip: disable early console by default

The early console is very useful for debugging. Alas, a misconfigured
early console seems to be halting/panicking OP-TEE OS.

Better have something al

plat-rockchip: disable early console by default

The early console is very useful for debugging. Alas, a misconfigured
early console seems to be halting/panicking OP-TEE OS.

Better have something always work possibly without console output (e.g.
if no FDT is passed to OP-TEE OS) than crashing without information.

The user can still enable the console if they want to for debugging
sessions.

This fixes OP-TEE OS crashing on RK3399 Puma which uses UART0 instead of
default UART2.

I've tested on PX30 and RK3588 by specifying a UART controller different
from the one that can be used by the device.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>

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plat-mediatek: add support for MT7987 SoC

Add OP-TEE support for the MT7987 SoC.

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-mediatek: add support for MT7981 SoC

Add OP-TEE support for the MT7981 SoC.

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-mediatek: add support for MT7986 SoC

Add OP-TEE support for the MT7986 SoC.

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

core: ffa: support fragmented memory transaction via S-EL2 SPMC

Add support to retrieve a fragmented memory transaction via an SPMC at
S-EL2.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.or

core: ffa: support fragmented memory transaction via S-EL2 SPMC

Add support to retrieve a fragmented memory transaction via an SPMC at
S-EL2.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@arm.com>

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core: ffa: harden memory transaction checks

Harden the checks for FF-A memory transaction operations. Check that
internal parts are well aligned and that we can handle fragmented
transactions.

Sign

core: ffa: harden memory transaction checks

Harden the checks for FF-A memory transaction operations. Check that
internal parts are well aligned and that we can handle fragmented
transactions.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@arm.com>

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plat-qcom: Add support for lemans SoC

Add support for lemans SoC with platform support tested on lemans EVK
platform also known as Qualcomm Dragonwing IQ-9075. More information
regarding this platfo

plat-qcom: Add support for lemans SoC

Add support for lemans SoC with platform support tested on lemans EVK
platform also known as Qualcomm Dragonwing IQ-9075. More information
regarding this platform can be found here [1].

[1] https://www.qualcomm.com/internet-of-things/products/iq9-series/iq-9075

Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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core: plat-imx: i.MX6 CA9 has no generic timer

The Cortex-A9 inside of the i.MX6Q/D/QP/DL/S/SL/SLL SoCs has no generic
timer support, but all variants should boot with 792Mhz out of the boot
rom. Se

core: plat-imx: i.MX6 CA9 has no generic timer

The Cortex-A9 inside of the i.MX6Q/D/QP/DL/S/SL/SLL SoCs has no generic
timer support, but all variants should boot with 792Mhz out of the boot
rom. Set the Generic Timer configuration variable to n and implement the
required plat_get_freq() call to support the udelay() calls.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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plat-corstone1000: swap GIC-600 for GIC-700 for Cortex-A320 variant

Switch the Cortex-A320 variant to use GIC-700 instead of GIC-600.
GIC-700 implements the Arm GICv4.1 architecture, so enable the
C

plat-corstone1000: swap GIC-600 for GIC-700 for Cortex-A320 variant

Switch the Cortex-A320 variant to use GIC-700 instead of GIC-600.
GIC-700 implements the Arm GICv4.1 architecture, so enable the
CFG_ARM_GICV4 compiler definition for the Corstone-1000 platform.

Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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gic: refactor implementation of GICv3 to add GICv4 support

Refactor the definitions of GICv3 to facilitate adding support for
GICv4 by:
* Add macro for registers frame sizes based on GIC versions.
*

gic: refactor implementation of GICv3 to add GICv4 support

Refactor the definitions of GICv3 to facilitate adding support for
GICv4 by:
* Add macro for registers frame sizes based on GIC versions.
* Add macro for number of frame count for GICR based on GICv3 or GICv4.
* Add single GICR region size definition (GIC_REDIST_REG_SIZE)
based on GIC version in platform independent include/drivers/gic.h
along with existing GIC_CPU_REG_SIZE and GIC_DIST_REG_SIZE
definitions.
* Amend usage of the now platform independent GIC_REDIST_REG_SIZE
as it no longer includes a multiplication by the number of core on
the target platform.
* Sort in ascending order the listing of GICR register definitions and
add comments to denote each definitions sections.
* Add definitions for each GICR frames.
* Ensure that all relevant code sections that compile for CFG_ARM_GICV3
also compile for CFG_ARM_GICV4.

Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-corstone1000: specify GIC version in plat specific conf.mk

The Generic Interrupt Controller architecture version is not core
specific. Therefore move the CFG_ARM_GICV3 definition from
cortex-a3

plat-corstone1000: specify GIC version in plat specific conf.mk

The Generic Interrupt Controller architecture version is not core
specific. Therefore move the CFG_ARM_GICV3 definition from
cortex-a320.mk file to the Corstone-1000 specific file.

Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-marvell: register DDR for dynamic shared memory

Register non-secure DDR memory region for Armada 7K/8K and Armada 3700
platforms to enable dynamic shared memory support.

Without this, U-Boot's

plat-marvell: register DDR for dynamic shared memory

Register non-secure DDR memory region for Armada 7K/8K and Armada 3700
platforms to enable dynamic shared memory support.

Without this, U-Boot's OP-TEE driver fails to probe with:
"OP-TEE capabilities mismatch"

The U-Boot OPTEE driver requires OPTEE_SMC_SEC_CAP_DYNAMIC_SHM capability,
which is advertised when core_mmu_nsec_ddr_is_defined() returns true.

The registered region starts after the reserved shared memory
(CFG_SHMEM_START + CFG_SHMEM_SIZE) and extends to the end of DRAM.
CFG_DDR_SIZE defaults to 2GB but can be overridden at build time for
boards with different memory configurations.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Set firewall for DTHEv2 RNG

Set firewall to protect DTHEv2 RNG from non-secure world.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: T Pratham <t-pratham@ti.com>
Review

plat-k3: drivers: Set firewall for DTHEv2 RNG

Set firewall to protect DTHEv2 RNG from non-secure world.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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plat-k3: drivers: Remove code to get firewall configs

The ti_crypto_init_rng_fwl() function gets firewall configurations
before setting new ones. This is pointless, since we are not using
the config

plat-k3: drivers: Remove code to get firewall configs

The ti_crypto_init_rng_fwl() function gets firewall configurations
before setting new ones. This is pointless, since we are not using
the configurations that we get anywhere. Therefore remove these blocks
of code.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Reviewed-by: T Pratham <t-pratham@ti.com>

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plat-k3: drivers: Refactor SA2UL RNG firewall setup

sa2ul_init() contains code to set firewall for SA2UL RNG. However,
almost the same code can also be used to firewall DTHEv2 RNG. Therefore
refacto

plat-k3: drivers: Refactor SA2UL RNG firewall setup

sa2ul_init() contains code to set firewall for SA2UL RNG. However,
almost the same code can also be used to firewall DTHEv2 RNG. Therefore
refactor this code into a separate function in the ti_sci driver.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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core: mm: add extra xlat table when core ASan is enabled

Enabling CFG_CORE_SANITIZE_KADDRESS increases MMU translation
table usage in multiple ways. In addition to ASan shadow regions,
the overall s

core: mm: add extra xlat table when core ASan is enabled

Enabling CFG_CORE_SANITIZE_KADDRESS increases MMU translation
table usage in multiple ways. In addition to ASan shadow regions,
the overall size of the core image grows, including code, data,
and stack mappings. This often leads to additional page table splits
and higher xlat table consumption.

Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@st.com>

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plat-stm32mp1: default enable CFG_STM32_DEBUG_ACCESS_PTA

In order to handle request on the debug configuration, default enable
CFG_STM32_DEBUG_ACCESS_PTA to embed the debug access PTA.

Signed-off-b

plat-stm32mp1: default enable CFG_STM32_DEBUG_ACCESS_PTA

In order to handle request on the debug configuration, default enable
CFG_STM32_DEBUG_ACCESS_PTA to embed the debug access PTA.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@st.com>

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core: arm: fix feat_pauth_implemented not consider QARMA3 algorithm

The feat_pauth_implemented function does not take
ID_AA64ISAR2_EL1.{GPA3,APA3} into account, which indicates the
processor support

core: arm: fix feat_pauth_implemented not consider QARMA3 algorithm

The feat_pauth_implemented function does not take
ID_AA64ISAR2_EL1.{GPA3,APA3} into account, which indicates the
processor supports the QARMA3.

According to Arm's documentation, ID_AA64ISAR1_EL1.{GPI,GPA,API,APA}
should be zero if ID_AA64ISAR2_EL1.{GPA3,APA3} are non-zero.
Therefore, OP-TEE wrongly reports that PAC is not available to TA
when the CPU uses QARMA3 algorithm.

This commit also introduces the register read function and related
definitions for ID_AA64ISAR2_EL1.

Signed-off-by: Leo Chen <shf.chen@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: atomic ftrace buffer map update

When switching sessions, that is, calling ts_push_current_session() or
ts_pop_current_session(), a foreign interrupt may save the current
thread. When this happ

core: atomic ftrace buffer map update

When switching sessions, that is, calling ts_push_current_session() or
ts_pop_current_session(), a foreign interrupt may save the current
thread. When this happens, the ftrace buffer mapping must be consistent
with the current session, or bad things, like OP-TEE core crashing or
corrupting TA memory, might occur. Fix this by masking foreign
interrupts while updating the linked list, and disable the ftrace buffer
while setting new TA mappings.

All mappings of a TA are removed if the TA crashes, even if user
mappings might still be active. Add checks in the functions accessing
the ftrace buffer that the buffer is accessible before accessing it to
avoid eventual OP-TEE core crashes.

Fixes: 17513217b24c ("ftrace: dump ftrace after every ta_entry")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>

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