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Searched refs:REG_MOD_BK00_60_L (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.c2536 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_Handshake()
2537 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
2538 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
2539 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
2540 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
2555 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
2577 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_Handshake()
2579 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
2924 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE) in MHal_PNL_Check_VBY1_Handshake_Status()
2995 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.c2536 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_Handshake()
2537 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
2538 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
2539 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
2540 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
2555 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
2577 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_Handshake()
2579 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
2924 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE) in MHal_PNL_Check_VBY1_Handshake_Status()
2995 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.c2866 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_Handshake()
2867 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
2868 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
2869 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
2870 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
2885 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
2907 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_Handshake()
2909 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
3363 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE) in MHal_PNL_Check_VBY1_Handshake_Status()
3450 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A DhalPNL.c3264 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_Handshake()
3265 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
3266 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
3267 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
3268 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
3283 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
3305 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_Handshake()
3307 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
3747 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE) in MHal_PNL_Check_VBY1_Handshake_Status()
3834 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.c3565 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_Handshake()
3566 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
3567 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
3568 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
3569 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
3584 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
3606 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_Handshake()
3608 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
4047 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE) in MHal_PNL_Check_VBY1_Handshake_Status()
4134 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.c3611 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_Handshake()
3612 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
3613 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
3614 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
3615 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
3630 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
3652 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_Handshake()
3654 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
4098 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE) in MHal_PNL_Check_VBY1_Handshake_Status()
4185 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.c3611 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_Handshake()
3612 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
3613 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
3614 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
3615 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
3630 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
3652 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_Handshake()
3654 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
4098 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE) in MHal_PNL_Check_VBY1_Handshake_Status()
4185 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.c4522 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_Handshake()
4523 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
4524 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
4525 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
4526 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
4541 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
4563 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_Handshake()
4565 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
5078 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE) in MHal_PNL_Check_VBY1_Handshake_Status()
5101 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.c4549 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value in MHal_PNL_VBY1_Handshake()
4550 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
4551 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
4552 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
4553 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
4568 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
4590 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE) in MHal_PNL_VBY1_Handshake()
4592 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE); in MHal_PNL_VBY1_Handshake()
5128 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE) in MHal_PNL_Check_VBY1_Handshake_Status()
5151 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE); in MHal_PNL_VBY1_Hardware_TrainingMode_En()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dhwreg_mod.h301 #define REG_MOD_BK00_60_L _PK_L_(0x00, 0x60) macro
/utopia/UTPA2-700.0.x/modules/xc/drv/pnl/
H A DdrvPNL.c766 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0000); in MDrv_PNL_SetPanelType()
/utopia/UTPA2-700.0.x/modules/xc/drv/pnl/include/
H A Dpnl_hwreg_utility2.h1892 #define REG_MOD_BK00_60_L _PK_L_(0x00, 0x60) macro