Searched refs:REG_CLKGEN0_STC_SRC_SYNTH (Results 1 – 14 of 14) sorted by relevance
156 #define REG_CLKGEN0_STC_SRC_SYNTH 0x0000 macro
494 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC0_SHIFT)); in HAL_TSP_Power()497 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC1_SHIFT)); in HAL_TSP_Power()
140 #define REG_CLKGEN0_STC_SRC_SYNTH 0x0000 macro
450 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC0_SHIFT)); in HAL_TSP_Power()453 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC1_SHIFT)); in HAL_TSP_Power()
149 #define REG_CLKGEN0_STC_SRC_SYNTH 0x0000 macro
599 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC0_SHIFT)); in HAL_TSP_Power()602 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC1_SHIFT)); in HAL_TSP_Power()
145 #define REG_CLKGEN0_STC_SRC_SYNTH 0x0000 macro
146 #define REG_CLKGEN0_STC_SRC_SYNTH 0x0000 macro
611 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC0_SHIFT)); in HAL_TSP_Power()614 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC1_SHIFT)); in HAL_TSP_Power()
523 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC0_SHIFT)); in HAL_TSP_Power()526 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC1_SHIFT)); in HAL_TSP_Power()