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Searched refs:MBRegBase (Results 1 – 25 of 145) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/sys/hal/mustang/sys/
H A DhalDMD_VD_MBX.c291 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
305 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
319 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
320 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
321 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
328 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
329 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
338 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
339 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
340 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/maldives/sys/
H A DhalDMD_VD_MBX.c291 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
305 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
319 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
320 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
321 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
328 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
329 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
338 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
339 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
340 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/M7821/sys/
H A DhalDMD_VD_MBX.c307 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
321 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
335 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
336 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
337 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
344 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
345 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
354 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
355 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
356 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/manhattan/sys/
H A DhalDMD_VD_MBX.c306 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
320 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
334 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
335 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
336 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
343 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
344 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
353 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
354 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
355 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/maserati/sys/
H A DhalDMD_VD_MBX.c307 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
321 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
335 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
336 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
337 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
344 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
345 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
354 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
355 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
356 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/mooney/sys/
H A DhalDMD_VD_MBX.c292 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
306 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
320 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
321 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
322 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
329 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
330 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
339 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
340 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
341 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/M7621/sys/
H A DhalDMD_VD_MBX.c307 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
321 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
335 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
336 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
337 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
344 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
345 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
354 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
355 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
356 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/macan/sys/
H A DhalDMD_VD_MBX.c306 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
320 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
334 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
335 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
336 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
343 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
344 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
353 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
354 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
355 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/maxim/sys/
H A DhalDMD_VD_MBX.c307 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
321 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
335 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
336 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
337 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
344 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
345 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
354 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
355 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
356 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/k7u/sys/
H A DhalDMD_VD_MBX.c308 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
322 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
336 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
337 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
338 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
345 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
346 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
355 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
356 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
357 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/k6/sys/
H A DhalDMD_VD_MBX.c308 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
322 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
336 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
337 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
338 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
345 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
346 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
355 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
356 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
357 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/mainz/sys/
H A DhalDMD_VD_MBX.c295 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
309 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
323 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
324 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
325 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
332 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
333 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
342 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
343 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
344 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/k6lite/sys/
H A DhalDMD_VD_MBX.c308 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
322 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
336 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
337 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
338 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
345 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
346 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
355 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
356 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
357 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/curry/sys/
H A DhalDMD_VD_MBX.c308 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
322 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
336 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
337 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
338 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
345 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
346 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
355 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
356 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
357 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/kano/sys/
H A DhalDMD_VD_MBX.c308 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
322 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
336 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
337 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
338 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
345 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
346 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
355 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
356 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
357 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/messi/sys/
H A DhalDMD_VD_MBX.c295 while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
309 while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF) // wait MB_CNTL set done in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
323 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
324 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
325 RIU_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
332 *u8Value = RIU_ReadByte(MBRegBase + 0x03); // REG_DATA get in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
333 RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
342 RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8)); // ADDR_H in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
343 RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr); // ADDR_L in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
344 RIU_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
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/utopia/UTPA2-700.0.x/modules/demodulator/drv/dmd/t3/Int_DVBT/
H A DINTERN_DVBT.c135 #define MBRegBase 0x110500//0x1033C0 macro
143 #define MBRegBase 0x112600 //Demod MailBox //mick macro
201 if (MDrv_ReadByte(MBRegBase + 0x00)) in INTERN_DVBT_ReadReg()
207 MDrv_WriteByte(MBRegBase + 0x02, (U8)(u16Addr >> 8)); // ADDR_H in INTERN_DVBT_ReadReg()
208 MDrv_WriteByte(MBRegBase + 0x01, (U8)u16Addr); // ADDR_L in INTERN_DVBT_ReadReg()
209 MDrv_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in INTERN_DVBT_ReadReg()
214 while(MDrv_ReadByte(MBRegBase + 0x00)!= 0xFF) // wait MB_CNTL set done in INTERN_DVBT_ReadReg()
226 *pu8Data = MDrv_ReadByte(MBRegBase + 0x03); // REG_DATA get in INTERN_DVBT_ReadReg()
227 MDrv_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT_ReadReg()
237 MDrv_WriteByte(MBRegBase + 0x02, (U8)(u16Addr >> 8)); // ADDR_H in INTERN_DVBT_WriteReg()
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/utopia/UTPA2-700.0.x/modules/demodulator/drv/dmd/t3/Int_DVBC/
H A DINTERN_DVBC.c132 #define MBRegBase 0x110500//0x1033C0 macro
183 if (MDrv_ReadByte(MBRegBase + 0x00)) in INTERN_DVBC_ReadReg()
189 MDrv_WriteByte(MBRegBase + 0x02, (U8)(u16Addr >> 8)); // ADDR_H in INTERN_DVBC_ReadReg()
190 MDrv_WriteByte(MBRegBase + 0x01, (U8)u16Addr); // ADDR_L in INTERN_DVBC_ReadReg()
191 MDrv_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode in INTERN_DVBC_ReadReg()
196 while(MDrv_ReadByte(MBRegBase + 0x00)!= 0xFF) // wait MB_CNTL set done in INTERN_DVBC_ReadReg()
208 *pu8Data = MDrv_ReadByte(MBRegBase + 0x03); // REG_DATA get in INTERN_DVBC_ReadReg()
209 MDrv_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBC_ReadReg()
219 MDrv_WriteByte(MBRegBase + 0x02, (U8)(u16Addr >> 8)); // ADDR_H in INTERN_DVBC_WriteReg()
220 MDrv_WriteByte(MBRegBase + 0x01, (U8)u16Addr); // ADDR_L in INTERN_DVBC_WriteReg()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_ISDBT.c147 #ifndef MBRegBase
148 #define MBRegBase 0x112600UL macro
186 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
187 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
188 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
189 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
196 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_WriteReg()
216 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_ReadReg()
217 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_ReadReg()
218 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02); in _MBX_ReadReg()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_DTMB.c197 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
198 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
199 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
200 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
207 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_WriteReg()
227 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_ReadReg()
228 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_ReadReg()
229 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02); in _MBX_ReadReg()
236 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_ReadReg()
239 *u8Data = HAL_DMD_RIU_ReadByte(MBRegBase + 0x10); in _MBX_ReadReg()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_DTMB.c200 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
201 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
202 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
203 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
210 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_WriteReg()
230 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_ReadReg()
231 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_ReadReg()
232 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02); in _MBX_ReadReg()
239 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_ReadReg()
242 *u8Data = HAL_DMD_RIU_ReadByte(MBRegBase + 0x10); in _MBX_ReadReg()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DTMB.c155 #define MBRegBase 0x112600 macro
230 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
231 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
232 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
233 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
240 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_WriteReg()
260 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_ReadReg()
261 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_ReadReg()
262 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02); in _MBX_ReadReg()
269 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_ReadReg()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DTMB.c155 #define MBRegBase 0x112600 macro
230 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
231 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
232 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
233 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
240 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_WriteReg()
260 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_ReadReg()
261 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_ReadReg()
262 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02); in _MBX_ReadReg()
269 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_ReadReg()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DTMB.c155 #define MBRegBase 0x112600 macro
230 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
231 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
232 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
233 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
240 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_WriteReg()
260 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_ReadReg()
261 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_ReadReg()
262 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02); in _MBX_ReadReg()
269 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_ReadReg()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DTMB.c155 #define MBRegBase 0x112600 macro
230 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
231 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
232 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
233 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
240 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_WriteReg()
260 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_ReadReg()
261 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_ReadReg()
262 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02); in _MBX_ReadReg()
269 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E); in _MBX_ReadReg()
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