1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_DTMB.h"
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 #define DMD_DTMB_CHIP_NIKON 0x00
112 #define DMD_DTMB_CHIP_NASA 0x01
113 #define DMD_DTMB_CHIP_MADISON 0x02
114 #define DMD_DTMB_CHIP_MONACO 0x03
115 #define DMD_DTMB_CHIP_MUJI 0x04
116 #define DMD_DTMB_CHIP_MONET 0x05
117 #define DMD_DTMB_CHIP_MANHATTAN 0x06
118 #define DMD_DTMB_CHIP_MESSI 0x07
119 #define DMD_DTMB_CHIP_MASERATI 0x08
120 #define DMD_DTMB_CHIP_MACAN 0x09
121
122 #if defined(CHIP_NIKON)
123 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
124 #elif defined(CHIP_NASA)
125 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NASA
126 #elif defined(CHIP_MADISON)
127 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MADISON
128 #elif defined(CHIP_MONACO)
129 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONACO
130 #elif defined(CHIP_MUJI)
131 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MUJI
132 #elif defined(CHIP_MONET)
133 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONET
134 #elif defined(CHIP_MANHATTAN)
135 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MANHATTAN
136 #elif defined(CHIP_MESSI)
137 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MESSI
138 #elif defined(CHIP_MASERATI)
139 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MASERATI
140 #elif defined(CHIP_MACAN)
141 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MACAN
142 #else
143 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
144 #endif
145
146 //-------------------------------------------------------------------------------------------------
147 // Local Defines
148 //-------------------------------------------------------------------------------------------------
149
150 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_DTMB_ResData->sDMD_DTMB_PriData.virtDMDBaseAddr + (addr) ) )
151 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_DTMB_ResData->sDMD_DTMB_PriData.virtDMDBaseAddr + (addr), val) )
152
153 #define HAL_INTERN_DTMB_DBINFO(y) //y
154
155 #define MBRegBase 0x112600
156 #define DMDMcuBase 0x103480
157
158 #define DTMB_REG_BASE 0x2600
159
160 #define DTMB_ACI_COEF_SIZE 112
161
162 #define DMD_DTMB_CHIP_ID_NASA 0x6E
163 #define DMD_DTMB_CHIP_ID_WALTZ 0x9C
164
165 //-------------------------------------------------------------------------------------------------
166 // Local Variables
167 //-------------------------------------------------------------------------------------------------
168
169 const MS_U8 INTERN_DTMB_table[] = {
170 #include "DMD_INTERN_DTMB.dat"
171 };
172
173 const MS_U8 INTERN_DTMB_6M_table[] = {
174 #include "DMD_INTERN_DTMB_6M.dat"
175 };
176
177 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
178 const MS_U8 INTERN_DTMB_table_Waltz[] = {
179 #include "DMD_INTERN_DTMB_Waltz.dat"
180 };
181
182 const MS_U8 INTERN_DTMB_6M_table_Waltz[] = {
183 #include "DMD_INTERN_DTMB_6M_Waltz.dat"
184 };
185 #endif
186
187 static MS_U8 _ACI_COEF_TABLE_FS24M_SR8M[DTMB_ACI_COEF_SIZE] = {
188 0x80, 0x06, 0x9f, 0xf4, 0x9f, 0xe8, 0x9f, 0xf0, 0x80, 0x09, 0x80, 0x1f, 0x80, 0x1d, 0x80, 0x03, 0x9f, 0xe3, 0x9f, 0xdc, 0x9f, 0xf7, 0x80, 0x1d, 0x80, 0x2c, 0x80, 0x12, 0x9f, 0xe2,
189 0x9f, 0xc9, 0x9f, 0xe2, 0x80, 0x1a, 0x80, 0x42, 0x80, 0x2f, 0x9f, 0xeb, 0x9f, 0xb2, 0x9f, 0xbe, 0x80, 0x0c, 0x80, 0x5b, 0x80, 0x5e, 0x80, 0x05, 0x9f, 0x9a, 0x9f, 0x81, 0x9f, 0xdf,
190 0x80, 0x6c, 0x80, 0xa7, 0x80, 0x45, 0x9f, 0x8c, 0x9f, 0x24, 0x9f, 0x84, 0x80, 0x7d, 0x81, 0x38, 0x80, 0xe3, 0x9f, 0x7b, 0x9e, 0x0e, 0x9e, 0x1f, 0x80, 0x87, 0x84, 0xa6, 0x88, 0x8c,
191 0x8a, 0x25, 0x80, 0x08, 0x80, 0x0b, 0x80, 0x0b, 0x80, 0x01, 0x9f, 0xee, 0x9f, 0xdf, 0x9f, 0xdb, 0x9f, 0xe8, 0x9f, 0xfd, 0x80, 0x0a};
192
193 static MS_U8 _ACI_COEF_TABLE_FS24M_SR6M[DTMB_ACI_COEF_SIZE] = {
194 0x9F, 0xF1, 0x9F, 0xFB, 0x80, 0x09, 0x80, 0x15, 0x80, 0x17, 0x80, 0x0D, 0x9F, 0xFB, 0x9F, 0xE9, 0x9F, 0xE2, 0x9F, 0xEC, 0x80, 0x04, 0x80, 0x1D, 0x80, 0x27, 0x80, 0x19, 0x9F, 0xFA,
195 0x9F, 0xD9, 0x9F, 0xCE, 0x9F, 0xE1, 0x80, 0x0C, 0x80, 0x35, 0x80, 0x42, 0x80, 0x24, 0x9F, 0xEA, 0x9F, 0xB6, 0x9F, 0xAA, 0x9F, 0xD6, 0x80, 0x26, 0x80, 0x6A, 0x80, 0x72, 0x80, 0x2E,
196 0x9F, 0xBF, 0x9F, 0x66, 0x9F, 0x65, 0x9F, 0xCE, 0x80, 0x71, 0x80, 0xED, 0x80, 0xE2, 0x80, 0x35, 0x9F, 0x2B, 0x9E, 0x5C, 0x9E, 0x72, 0x9F, 0xCA, 0x82, 0x3B, 0x85, 0x13, 0x87, 0x59,
197 0x88, 0x38, 0x80, 0x00, 0x80, 0x00, 0x80, 0x01, 0x80, 0x02, 0x80, 0x02, 0x80, 0x00, 0x9F, 0xFC, 0x9F, 0xF6, 0x9F, 0xF0, 0x9F, 0xED};
198
199 //-------------------------------------------------------------------------------------------------
200 // Global Variables
201 //-------------------------------------------------------------------------------------------------
202
203 extern MS_U8 u8DMD_DTMB_DMD_ID;
204
205 extern DMD_DTMB_ResData *psDMD_DTMB_ResData;
206
207 //-------------------------------------------------------------------------------------------------
208 // Local Functions
209 //-------------------------------------------------------------------------------------------------
_HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)210 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
211 {
212 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
213 }
214
_HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)215 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
216 {
217 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
218 }
219
220 //static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
221 //{
222 // _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
223 //}
224
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)225 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
226 {
227 MS_U8 u8CheckCount;
228 MS_U8 u8CheckFlag;
229
230 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
231 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
232 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data);
233 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01);
234
235 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
236 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
237
238 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
239 {
240 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
241 if ((u8CheckFlag&0x01)==0)
242 break;
243 MsOS_DelayTask(1);
244 }
245
246 if (u8CheckFlag&0x01)
247 {
248 printf("ERROR: DTMB INTERN DEMOD MBX WRITE TIME OUT!\n");
249 return FALSE;
250 }
251
252 return TRUE;
253 }
254
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)255 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
256 {
257 MS_U8 u8CheckCount;
258 MS_U8 u8CheckFlag;
259
260 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
261 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
262 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
263
264 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
265 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
266
267 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
268 {
269 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
270 if ((u8CheckFlag&0x02)==0)
271 {
272 *u8Data = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x10);
273 break;
274 }
275 MsOS_DelayTask(1);
276 }
277
278 if (u8CheckFlag&0x02)
279 {
280 printf("ERROR: DTMB INTERN DEMOD MBX READ TIME OUT!\n");
281 return FALSE;
282 }
283
284 return TRUE;
285 }
286
287 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NIKON)
_HAL_INTERN_DTMB_InitClk(void)288 static void _HAL_INTERN_DTMB_InitClk(void)
289 {
290 MS_U8 u8Val = 0;
291
292 printf("--------------DMD_DTMB_CHIP_NIKON--------------\n");
293
294 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
295 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
296
297 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
298 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
299 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
300 _HAL_DMD_RIU_WriteByte(0x103300, 0x14);
301 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
302 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
303 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
304 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
305
306 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
307 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
308 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
309 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
310 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
311 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
312 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
313 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
314 _HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
315 _HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
316 //_HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
317 _HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
318 _HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
319 _HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
320 _HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
321 _HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
322 _HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
323 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
324 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
325 _HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
326 _HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
327 _HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
328 _HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
329 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
330 _HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
331 _HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
332 _HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
333 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
334 _HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
335
336 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
337 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
338 }
339 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
_HAL_INTERN_DTMB_InitClk(void)340 static void _HAL_INTERN_DTMB_InitClk(void)
341 {
342 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
343
344 MS_U8 u8Val = 0;
345
346 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
347 {
348 printf("--------------DMD_DTMB_CHIP_WALTZ--------------\n");
349
350 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
351 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
352
353 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
354 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
355
356 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
357 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
358
359 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
360 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
361 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
362 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
363
364 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
365 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
366
367 _HAL_DMD_RIU_WriteByte(0x111f49, 0xcc);
368 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
369
370 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
371 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
372 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
373 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
374 _HAL_DMD_RIU_WriteByte(0x111f75, 0x00);
375 _HAL_DMD_RIU_WriteByte(0x111f74, 0x00);
376 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
377 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
378
379 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
380 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
381 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
382 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
383 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
384 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
385 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
386 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
387
388 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
389 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
390 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x00);
391 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x00);
392 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
393 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
394
395 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
396 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
397
398 _HAL_DMD_RIU_WriteByte(0x111f79, 0x00);
399 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
400
401 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
402 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
403
404 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
405 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
406 }
407 else
408 {
409 printf("--------------DMD_DTMB_CHIP_NASA--------------\n");
410
411 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
412 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
413
414 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
415 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
416 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
417 _HAL_DMD_RIU_WriteByte(0x103300, 0x14);
418 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
419 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
420 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
421 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
422
423 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
424 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
425 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
426 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
427 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
428 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
429 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
430 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
431 _HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
432 _HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
433 //_HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
434 _HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
435 _HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
436 _HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
437 _HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
438 _HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
439 _HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
440 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
441 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
442 _HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
443 _HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
444 _HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
445 _HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
446 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
447 _HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
448 _HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
449 _HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
450 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
451 _HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
452
453 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
454 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
455 }
456 }
457 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
_HAL_INTERN_DTMB_InitClk(void)458 static void _HAL_INTERN_DTMB_InitClk(void)
459 {
460 MS_U8 u8Val = 0;
461
462 printf("--------------DMD_DTMB_CHIP_MADISON--------------\n");
463
464 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
465 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
466
467 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
468 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
469 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
470 _HAL_DMD_RIU_WriteByte(0x103300, 0x14);
471 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
472 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
473 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
474 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
475
476 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
477 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
478
479 //carl
480 _HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
481 _HAL_DMD_RIU_WriteByte(0x111f14, 0x01);
482 _HAL_DMD_RIU_WriteByte(0x111f17, 0x01);
483 _HAL_DMD_RIU_WriteByte(0x111f16, 0x01);
484
485 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
486 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
487 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
488 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
489 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
490 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
491 _HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
492 _HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
493
494 //carl
495 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
496 _HAL_DMD_RIU_WriteByte(0x111f22, 0x04);
497
498 //_HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
499 _HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
500 _HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
501 _HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
502 _HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
503 _HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
504 _HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
505 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
506 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
507 _HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
508 _HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
509 _HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
510 _HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
511 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
512 _HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
513 _HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
514 _HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
515 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
516 _HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
517
518 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
519 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
520 }
521 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO)
_HAL_INTERN_DTMB_InitClk(void)522 static void _HAL_INTERN_DTMB_InitClk(void)
523 {
524 MS_U8 u8Val = 0;
525
526 printf("--------------DMD_DTMB_CHIP_MONACO--------------\n");
527
528 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
529 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
530
531 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
532 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
533
534 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
535 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
536
537 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
538 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
539 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
540 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
541
542 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
543 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
544
545 //carl
546 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
547 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
548
549 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
550 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
551 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
552 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
553 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
554 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
555 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
556 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
557 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
558 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
559
560 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
561 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
562 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
563 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
564
565 //carl
566 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
567 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
568 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
569 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
570
571 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
572 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
573
574 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
575
576 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
577 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
578 }
579 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI)
_HAL_INTERN_DTMB_InitClk(void)580 static void _HAL_INTERN_DTMB_InitClk(void)
581 {
582 MS_U8 u8Val = 0;
583
584 printf("--------------DMD_DTMB_CHIP_MUJI--------------\n");
585
586 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
587 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
588
589 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
590 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
591
592 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
593 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
594
595 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
596 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
597 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
598 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
599 _HAL_DMD_RIU_WriteByte(0x103302, 0x01); //MUJI add
600 _HAL_DMD_RIU_WriteByte(0x103302, 0x00); //MUJI add
601
602 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
603 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
604
605 //carl
606 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
607 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
608
609 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
610 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
611 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
612 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
613 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
614 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
615 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
616 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
617 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
618 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
619
620 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
621 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
622 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
623 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
624
625 //carl
626 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
627 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
628 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
629 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
630
631 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
632 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
633
634 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
635
636 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04); //MUJI add
637 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00); //MuJI add
638
639 _HAL_DMD_RIU_WriteByte(0x112091, 0x2f); //SRAM power saving
640 _HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
641
642 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
643 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
644 }
645 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONET)
_HAL_INTERN_DTMB_InitClk(void)646 static void _HAL_INTERN_DTMB_InitClk(void)
647 {
648 MS_U8 u8Val = 0;
649
650 printf("--------------DMD_DTMB_CHIP_MONET--------------\n");
651
652 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
653 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
654
655 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
656 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
657
658 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
659 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
660
661 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
662 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
663 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
664 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
665 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
666 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
667
668 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
669 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
670
671 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
672 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
673
674 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
675 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
676 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
677 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
678
679 _HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
680 _HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
681
682 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
683 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
684 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
685 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
686 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
687 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
688
689 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
690 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
691 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
692 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
693
694 //carl
695 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
696 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
697
698 _HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
699 _HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
700
701
702 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
703 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
704
705 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
706 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
707
708 _HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
709 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
710
711 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
712 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
713
714 // _HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
715 // _HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
716
717 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
718 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
719 }
720 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MANHATTAN)
_HAL_INTERN_DTMB_InitClk(void)721 static void _HAL_INTERN_DTMB_InitClk(void)
722 {
723 MS_U8 u8Val = 0;
724
725 printf("--------------DMD_DTMB_CHIP_MANHATTAN--------------\n");
726
727 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
728 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
729
730 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
731 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
732
733 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
734 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
735
736 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
737 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
738 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
739 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
740 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
741 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
742
743 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
744 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
745
746 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
747 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
748
749 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
750 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
751 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
752 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
753
754 // _HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
755 // _HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
756
757 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
758 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
759 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
760 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
761 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
762 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
763
764 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
765 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
766 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
767 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
768
769 //carl
770 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
771 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
772
773 // _HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
774 _HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
775
776
777 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
778 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
779
780 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
781 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
782
783 _HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
784 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
785
786 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
787 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
788
789 _HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
790 _HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
791
792 _HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
793 _HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
794
795 _HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
796 _HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
797
798 _HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
799 _HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
800
801 _HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
802 _HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
803
804 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
805 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
806
807
808 // _HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
809 // _HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
810
811 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
812 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
813 }
814 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MESSI)
_HAL_INTERN_DTMB_InitClk(void)815 static void _HAL_INTERN_DTMB_InitClk(void)
816 {
817 MS_U8 u8Val = 0;
818
819 printf("--------------DMD_DTMB_CHIP_MESSI--------------\n");
820
821 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
822 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
823
824 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
825 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
826
827 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
828 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
829
830 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
831 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
832 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
833 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
834 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
835 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
836
837 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
838 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
839
840 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
841 //_HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
842 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);//MESSI only?
843
844 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
845 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
846 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
847 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
848
849 // _HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
850 // _HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
851
852 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
853 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
854 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
855 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
856 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
857 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
858
859 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
860 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
861 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
862 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
863
864 //carl
865 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
866 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
867
868 // _HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
869 _HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
870
871
872 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
873 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
874
875 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
876 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
877
878 _HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
879 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
880
881 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
882 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
883
884 _HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
885 _HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
886
887 _HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
888 _HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
889
890 _HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
891 _HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
892
893 _HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
894 _HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
895
896 _HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
897 _HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
898
899 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
900 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
901
902
903 // _HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
904 // _HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
905
906 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
907 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
908 }
909 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
_HAL_INTERN_DTMB_InitClk(void)910 static void _HAL_INTERN_DTMB_InitClk(void)
911 {
912 MS_U8 u8Val = 0;
913
914 printf("--------------DMD_DTMB_CHIP_MASERATI_MACAN--------------\n");
915
916 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
917 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
918
919 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
920
921 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
922 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
923
924 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
925 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
926
927 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
928 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
929
930 //_HAL_DMD_RIU_WriteByte(0x103315, 0x00);
931 //_HAL_DMD_RIU_WriteByte(0x103314, 0x00);
932
933 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
934 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
935
936 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
937 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
938
939 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
940 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
941
942 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
943
944 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
945 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
946
947 _HAL_DMD_RIU_WriteByte(0x111f69, 0xCC);
948 _HAL_DMD_RIU_WriteByte(0x111f68, 0x11);
949
950 _HAL_DMD_RIU_WriteByte(0x152923, 0x00);
951 _HAL_DMD_RIU_WriteByte(0x152922, 0x14);
952
953 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
954 _HAL_DMD_RIU_WriteByte(0x111f24, 0x00);
955
956 _HAL_DMD_RIU_WriteByte(0x152973, 0x00);
957 _HAL_DMD_RIU_WriteByte(0x152972, 0x00);
958
959 _HAL_DMD_RIU_WriteByte(0x152975, 0x00);
960 _HAL_DMD_RIU_WriteByte(0x152974, 0x00);
961
962 _HAL_DMD_RIU_WriteByte(0x152977, 0x0c);
963 _HAL_DMD_RIU_WriteByte(0x152976, 0x0c);
964
965 _HAL_DMD_RIU_WriteByte(0x152961, 0x00);
966 _HAL_DMD_RIU_WriteByte(0x152960, 0x00);
967
968 _HAL_DMD_RIU_WriteByte(0x152963, 0x00);
969 _HAL_DMD_RIU_WriteByte(0x152962, 0x00);
970
971 _HAL_DMD_RIU_WriteByte(0x152965, 0x00);
972 _HAL_DMD_RIU_WriteByte(0x152964, 0x00);
973
974 _HAL_DMD_RIU_WriteByte(0x152969, 0x00);
975 _HAL_DMD_RIU_WriteByte(0x152968, 0x00);
976
977 _HAL_DMD_RIU_WriteByte(0x15296B, 0x44);
978 _HAL_DMD_RIU_WriteByte(0x15296A, 0x44);
979
980 _HAL_DMD_RIU_WriteByte(0x15297a, 0x00);
981
982 _HAL_DMD_RIU_WriteByte(0x15296d, 0x00);
983 _HAL_DMD_RIU_WriteByte(0x15296c, 0xc4);
984
985 _HAL_DMD_RIU_WriteByte(0x152971, 0x00);
986 _HAL_DMD_RIU_WriteByte(0x152970, 0x04);
987
988 _HAL_DMD_RIU_WriteByte(0x152979, 0x00);
989 _HAL_DMD_RIU_WriteByte(0x152978, 0x00);
990
991 _HAL_DMD_RIU_WriteByte(0x152951, 0x04);
992 _HAL_DMD_RIU_WriteByte(0x152950, 0x00);
993
994 _HAL_DMD_RIU_WriteByte(0x152981, 0x88);
995 _HAL_DMD_RIU_WriteByte(0x152980, 0x88);
996
997 _HAL_DMD_RIU_WriteByte(0x152983, 0xc8);
998 _HAL_DMD_RIU_WriteByte(0x152982, 0x88);
999
1000 _HAL_DMD_RIU_WriteByte(0x152985, 0x88);
1001 _HAL_DMD_RIU_WriteByte(0x152984, 0x88);
1002
1003 _HAL_DMD_RIU_WriteByte(0x152987, 0x08);
1004 _HAL_DMD_RIU_WriteByte(0x152986, 0x8c);
1005
1006 _HAL_DMD_RIU_WriteByte(0x111f75, 0x81);
1007 _HAL_DMD_RIU_WriteByte(0x111f74, 0x81);
1008
1009 _HAL_DMD_RIU_WriteByte(0x111f77, 0x81);
1010 _HAL_DMD_RIU_WriteByte(0x111f76, 0x88);
1011
1012 _HAL_DMD_RIU_WriteByte(0x15298d, 0x44);
1013 _HAL_DMD_RIU_WriteByte(0x15298c, 0x00);
1014
1015 _HAL_DMD_RIU_WriteByte(0x15298f, 0x88);
1016 _HAL_DMD_RIU_WriteByte(0x15298e, 0x88);
1017
1018 _HAL_DMD_RIU_WriteByte(0x152991, 0xc8);
1019 _HAL_DMD_RIU_WriteByte(0x152990, 0x88);
1020
1021 _HAL_DMD_RIU_WriteByte(0x152993, 0x11);
1022 _HAL_DMD_RIU_WriteByte(0x152992, 0x18);
1023
1024 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x18);
1025 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x11);
1026
1027 _HAL_DMD_RIU_WriteByte(0x111f79, 0x11);
1028 _HAL_DMD_RIU_WriteByte(0x111f78, 0x88);
1029
1030 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x18);
1031 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1032
1033 _HAL_DMD_RIU_WriteByte(0x111f89, 0x00);
1034 _HAL_DMD_RIU_WriteByte(0x111f88, 0x00);
1035
1036 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1037 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);
1038
1039 _HAL_DMD_RIU_WriteByte(0x111f31, 0x18);
1040
1041
1042 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1043 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1044 }
1045 #else
_HAL_INTERN_DTMB_InitClk(void)1046 static void _HAL_INTERN_DTMB_InitClk(void)
1047 {
1048 printf("--------------DMD_DTMB_CHIP_NONE--------------\n");
1049 }
1050 #endif
1051
_HAL_INTERN_DTMB_Ready(void)1052 static MS_BOOL _HAL_INTERN_DTMB_Ready(void)
1053 {
1054 MS_U8 udata = 0x00;
1055
1056 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
1057
1058 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1059 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1060
1061 MsOS_DelayTask(1);
1062
1063 udata = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
1064
1065 if (udata) return FALSE;
1066
1067 return TRUE;
1068 }
1069
_HAL_INTERN_DTMB_Download(void)1070 static MS_BOOL _HAL_INTERN_DTMB_Download(void)
1071 {
1072 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1073 MS_U8 udata = 0x00;
1074 MS_U16 i = 0;
1075 MS_U16 fail_cnt = 0;
1076 MS_U8 u8TmpData;
1077 MS_U16 u16AddressOffset;
1078 const MS_U8 *DTMB_table;
1079 MS_U16 u16Lib_size;
1080
1081 if (pRes->sDMD_DTMB_PriData.bDownloaded)
1082 {
1083 if (_HAL_INTERN_DTMB_Ready())
1084 {
1085 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1086 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
1087 MsOS_DelayTask(20);
1088 return TRUE;
1089 }
1090 }
1091
1092 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1093 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1094 {
1095 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1096 {
1097 DTMB_table = &INTERN_DTMB_6M_table_Waltz[0];
1098 u16Lib_size = sizeof(INTERN_DTMB_6M_table_Waltz);
1099 }
1100 else
1101 {
1102 DTMB_table = &INTERN_DTMB_table_Waltz[0];
1103 u16Lib_size = sizeof(INTERN_DTMB_table_Waltz);
1104 }
1105 }
1106 else
1107 {
1108 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1109 {
1110 DTMB_table = &INTERN_DTMB_6M_table[0];
1111 u16Lib_size = sizeof(INTERN_DTMB_6M_table);
1112 }
1113 else
1114 {
1115 DTMB_table = &INTERN_DTMB_table[0];
1116 u16Lib_size = sizeof(INTERN_DTMB_table);
1117 }
1118 }
1119 #else
1120 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1121 {
1122 DTMB_table = &INTERN_DTMB_6M_table[0];
1123 u16Lib_size = sizeof(INTERN_DTMB_6M_table);
1124 }
1125 else
1126 {
1127 DTMB_table = &INTERN_DTMB_table[0];
1128 u16Lib_size = sizeof(INTERN_DTMB_table);
1129 }
1130 #endif
1131
1132 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1133 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1134
1135 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1136
1137 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1138 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1139 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1140 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1141
1142 //// Load code thru VDMCU_IF ////
1143 HAL_INTERN_DTMB_DBINFO(printf(">Load Code...\n"));
1144
1145 for (i = 0; i < u16Lib_size; i++)
1146 {
1147 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, DTMB_table[i]); // write data to VD MCU 51 code sram
1148 }
1149
1150 //// Content verification ////
1151 HAL_INTERN_DTMB_DBINFO(printf(">Verify Code...\n"));
1152
1153 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1154 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1155
1156 for (i = 0; i < u16Lib_size; i++)
1157 {
1158 udata = _HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
1159
1160 if (udata != DTMB_table[i])
1161 {
1162 HAL_INTERN_DTMB_DBINFO(printf(">fail add = 0x%x\n", i));
1163 HAL_INTERN_DTMB_DBINFO(printf(">code = 0x%x\n", DTMB_table[i]));
1164 HAL_INTERN_DTMB_DBINFO(printf(">data = 0x%x\n", udata));
1165
1166 if (fail_cnt++ > 10)
1167 {
1168 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode fail!"));
1169 return FALSE;
1170 }
1171 }
1172 }
1173
1174 u16AddressOffset = (DTMB_table[0x400] << 8)|DTMB_table[0x401];
1175
1176 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1177 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1178
1179 //pRes->sDMD_DTMB_InitData.u16IF_KHZ=5000; //for temp solution wayne@20151004
1180 //pRes->sDMD_DTMB_InitData.bIQSwap=1;
1181 //pRes->sDMD_DTMB_InitData.u32TdiStartAddr=0x01598000;
1182
1183 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16IF_KHZ;
1184 HAL_INTERN_DTMB_DBINFO(printf("u16IF_KHZ=%d\n",pRes->sDMD_DTMB_InitData.u16IF_KHZ));
1185 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1186 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16IF_KHZ >> 8);
1187 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1188 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.bIQSwap;
1189 HAL_INTERN_DTMB_DBINFO(printf("bIQSwap=%d\n",pRes->sDMD_DTMB_InitData.bIQSwap));
1190 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1191 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE;
1192 HAL_INTERN_DTMB_DBINFO(printf("u16AGC_REFERENCE=%X\n",pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE));
1193 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1194 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE >> 8);
1195 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1196 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u32TdiStartAddr;
1197 HAL_INTERN_DTMB_DBINFO(printf("u32TdiStartAddr=%X\n",pRes->sDMD_DTMB_InitData.u32TdiStartAddr));
1198 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1199 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 8);
1200 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1201 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 16);
1202 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1203 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 24);
1204 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1205 u8TmpData = (MS_U8)pRes->sDMD_DTMB_PriData.eLastType;
1206 HAL_INTERN_DTMB_DBINFO(printf("eLastType=%d\n",pRes->sDMD_DTMB_PriData.eLastType));
1207 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1208
1209 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1210 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1211
1212 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1213
1214 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1215 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1216
1217 pRes->sDMD_DTMB_PriData.bDownloaded = true;
1218
1219 MsOS_DelayTask(20);
1220
1221 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode done."));
1222
1223 return TRUE;
1224 }
1225
_HAL_INTERN_DTMB_FWVERSION(void)1226 static void _HAL_INTERN_DTMB_FWVERSION(void)
1227 {
1228 MS_U8 data1,data2,data3;
1229
1230 _MBX_ReadReg(0x20C4, &data1);
1231 _MBX_ReadReg(0x20C5, &data2);
1232 _MBX_ReadReg(0x20C6, &data3);
1233
1234 HAL_INTERN_DTMB_DBINFO(printf("INTERN_DTMB_FW_VERSION:%x.%x.%x\n", data1, data2, data3));
1235 }
1236
_HAL_INTERN_DTMB_Exit(void)1237 static MS_BOOL _HAL_INTERN_DTMB_Exit(void)
1238 {
1239 MS_U8 u8CheckCount = 0;
1240
1241 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
1242
1243 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1244 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1245
1246 while ((_HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
1247 {
1248 MsOS_DelayTaskUs(10);
1249
1250 if (u8CheckCount++ == 0xFF)
1251 {
1252 printf(">> DTMB Exit Fail!\n");
1253 return FALSE;
1254 }
1255 }
1256
1257 printf(">> DTMB Exit Ok!\n");
1258
1259 return TRUE;
1260 }
1261
_HAL_INTERN_DTMB_SoftReset(void)1262 static MS_BOOL _HAL_INTERN_DTMB_SoftReset(void)
1263 {
1264 MS_U8 u8Data = 0;
1265
1266 //Reset FSM
1267 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
1268
1269 while (u8Data!=0x02)
1270 {
1271 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1272 }
1273
1274 return TRUE;
1275 }
1276
_HAL_INTERN_DTMB_SetACICoef(void)1277 static MS_BOOL _HAL_INTERN_DTMB_SetACICoef(void)
1278 {
1279 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1280
1281 MS_U8 *ACI_table;
1282 MS_U8 i;
1283 MS_U16 u16AddressOffset;
1284
1285 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB)
1286 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1287 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M)
1288 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1289 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1290 ACI_table = &_ACI_COEF_TABLE_FS24M_SR6M[0];
1291 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1292 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1293 else ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1294
1295 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1296 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1297
1298 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1299
1300 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1301 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1302 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1303 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1304
1305 //SET SR value
1306 u16AddressOffset = ((INTERN_DTMB_table[0x400] << 8)|INTERN_DTMB_table[0x401]) + 10;
1307 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1308 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1309 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)pRes->sDMD_DTMB_PriData.eLastType);
1310
1311 //set ACI coefficient
1312 u16AddressOffset = ((INTERN_DTMB_table[0x40A] << 8)|INTERN_DTMB_table[0x40B]);
1313 u16AddressOffset = ((INTERN_DTMB_table[u16AddressOffset] << 8)|INTERN_DTMB_table[u16AddressOffset+1]);
1314 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1315 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1316 for (i = 0; i < DTMB_ACI_COEF_SIZE; i++)
1317 {
1318 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ACI_table[i]); // write data to VD MCU 51 code sram
1319 }
1320
1321 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1322 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1323
1324 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1325
1326 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1327 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1328
1329 MsOS_DelayTask(20);
1330
1331 return TRUE;
1332 }
1333
_HAL_INTERN_DTMB_SetDtmbMode(void)1334 static MS_BOOL _HAL_INTERN_DTMB_SetDtmbMode(void)
1335 {
1336 if (_MBX_WriteReg(0x20C2, 0x03)==FALSE) return FALSE;
1337 return _MBX_WriteReg(0x20C0, 0x04);
1338 }
1339
_HAL_INTERN_DTMB_SetModeClean(void)1340 static MS_BOOL _HAL_INTERN_DTMB_SetModeClean(void)
1341 {
1342 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1343 return _MBX_WriteReg(0x20C0, 0x00);
1344 }
1345
_HAL_INTERN_DTMB_Set_QAM_SR(void)1346 static MS_BOOL _HAL_INTERN_DTMB_Set_QAM_SR(void)
1347 {
1348 if (_MBX_WriteReg(0x20C2, 0x01)==FALSE) return FALSE;
1349 return _MBX_WriteReg(0x20C0, 0x04);
1350 }
1351
_HAL_INTERN_DTMB_AGCLock(void)1352 static MS_BOOL _HAL_INTERN_DTMB_AGCLock(void)
1353 {
1354 MS_U8 data = 0;
1355
1356 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1357 _MBX_ReadReg(0x2829, &data);//AGC_LOCK
1358 #else
1359 _MBX_ReadReg(0x271D, &data);//AGC_LOCK
1360 #endif
1361 if (data&0x01)
1362 {
1363 return TRUE;
1364 }
1365 else
1366 {
1367 return FALSE;
1368 }
1369 }
1370
_HAL_INTERN_DTMB_PNP_Lock(void)1371 static MS_BOOL _HAL_INTERN_DTMB_PNP_Lock(void)
1372 {
1373 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1374 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1375 #endif
1376
1377 MS_U8 data = 0;
1378 MS_U8 data1 = 0;
1379
1380 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1381 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1382 {
1383 _MBX_ReadReg(0x3BBA, &data);
1384 _MBX_ReadReg(0x3C49, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1385 }
1386 else
1387 {
1388 _MBX_ReadReg(0x22BA, &data);
1389 _MBX_ReadReg(0x2349, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1390 }
1391 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1392 _MBX_ReadReg(0x37BA, &data);
1393 _MBX_ReadReg(0x3849, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1394 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1395 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1396 _MBX_ReadReg(0x11BA, &data);
1397 _MBX_ReadReg(0x1249, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1398 #else
1399 _MBX_ReadReg(0x3BBA, &data);
1400 _MBX_ReadReg(0x3C49, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1401 #endif
1402 #else
1403 _MBX_ReadReg(0x22BA, &data);
1404 _MBX_ReadReg(0x2349, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1405 #endif
1406
1407 if (((data&0x02) == 0x02)&&((data1&0x20)==0x20))
1408 {
1409 return TRUE;
1410 }
1411 else
1412 {
1413 return FALSE;
1414 }
1415 }
1416
_HAL_INTERN_DTMB_FEC_Lock(void)1417 static MS_BOOL _HAL_INTERN_DTMB_FEC_Lock(void)
1418 {
1419 MS_U8 u8state=0;
1420
1421
1422 _MBX_ReadReg(0x20C1, &u8state);
1423
1424 if ((u8state >= 0x62)&& (u8state <= 0xF0))
1425 {
1426 return TRUE;
1427 }
1428 else
1429 {
1430 return FALSE;
1431 }
1432 }
1433
_HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO * psDtmbGetModulation)1434 static MS_BOOL _HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO *psDtmbGetModulation)
1435 {
1436 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1437
1438 MS_U8 CM, QAM, IL, CR, SiNR;
1439 MS_U8 data_L = 0;
1440 MS_U8 data_H = 0;
1441
1442 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1443 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1444 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1445 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1446 {
1447 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1448 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1449 {
1450 _MBX_ReadReg(0x3B90, &data_L);
1451 _MBX_ReadReg(0x3B91, &data_H);
1452 }
1453 else
1454 {
1455 _MBX_ReadReg(0x2290, &data_L);
1456 _MBX_ReadReg(0x2291, &data_H);
1457 }
1458 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1459 _MBX_ReadReg(0x3790, &data_L);
1460 _MBX_ReadReg(0x3791, &data_H);
1461 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1462 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1463 _MBX_ReadReg(0x1190, &data_L);
1464 _MBX_ReadReg(0x1191, &data_H);
1465 #else
1466 _MBX_ReadReg(0x3B90, &data_L);
1467 _MBX_ReadReg(0x3B91, &data_H);
1468 #endif
1469 #else
1470 _MBX_ReadReg(0x2290, &data_L);
1471 _MBX_ReadReg(0x2291, &data_H);
1472 #endif
1473
1474 if (data_L & 0x1)
1475 {
1476 CR = (data_L >> 6) & 0x03;
1477 IL = (data_L >> 3) & 0x01;
1478 QAM = (data_L >> 4) & 0x03;
1479 SiNR = (data_L >> 2) & 0x01;
1480 CM = (data_L >> 1) & 0x01;
1481 }
1482 else
1483 {
1484 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1485 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1486 {
1487 _MBX_ReadReg(0x3B9E, &data_L);
1488 _MBX_ReadReg(0x3B9F, &data_H);
1489 }
1490 else
1491 {
1492 _MBX_ReadReg(0x229E, &data_L);
1493 _MBX_ReadReg(0x229F, &data_H);
1494 }
1495 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1496 _MBX_ReadReg(0x379E, &data_L);
1497 _MBX_ReadReg(0x379F, &data_H);
1498 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1499 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1500 _MBX_ReadReg(0x119E, &data_L);
1501 _MBX_ReadReg(0x119F, &data_H);
1502 #else
1503 _MBX_ReadReg(0x3B9E, &data_L);
1504 _MBX_ReadReg(0x3B9F, &data_H);
1505 #endif
1506 #else
1507 _MBX_ReadReg(0x229E, &data_L);
1508 _MBX_ReadReg(0x229F, &data_H);
1509 #endif
1510
1511 CR = (data_H >> 4) & 0x03;
1512 IL = (data_H >> 6) & 0x01;
1513 QAM = (data_H >> 2) & 0x03;
1514 SiNR = (data_H >> 1) & 0x01;
1515 CM = (data_H) & 0x01;
1516 }
1517
1518 #if 1//def MSOS_TYPE_LINUX_KERNEL
1519 if (CR == 0)
1520 psDtmbGetModulation->fSiCodeRate = 4;
1521 else if (CR == 1)
1522 psDtmbGetModulation->fSiCodeRate = 6;
1523 else if (CR == 2)
1524 psDtmbGetModulation->fSiCodeRate = 8;
1525 #else
1526 if (CR == 0)
1527 psDtmbGetModulation->fSiCodeRate = 0.4;
1528 else if (CR == 1)
1529 psDtmbGetModulation->fSiCodeRate = 0.6;
1530 else if (CR == 2)
1531 psDtmbGetModulation->fSiCodeRate = 0.8;
1532 #endif
1533
1534 if (IL == 0)
1535 psDtmbGetModulation->u8SiInterLeaver = 240;
1536 else
1537 psDtmbGetModulation->u8SiInterLeaver = 720;
1538
1539 if (QAM == 0)
1540 psDtmbGetModulation->u8SiQamMode = 4;
1541 else if (QAM == 1)
1542 psDtmbGetModulation->u8SiQamMode = 16;
1543 else if (QAM == 2)
1544 psDtmbGetModulation->u8SiQamMode = 32;
1545 else if (QAM == 3)
1546 psDtmbGetModulation->u8SiQamMode = 64;
1547
1548 psDtmbGetModulation->u8SiCarrierMode = CM; // 0:Multi, 1:Single
1549 psDtmbGetModulation->u8SiNR = SiNR;
1550 }
1551 else
1552 {
1553 }
1554
1555 return TRUE;
1556 }
1557
_HAL_INTERN_DTMB_ReadIFAGC(void)1558 static MS_U8 _HAL_INTERN_DTMB_ReadIFAGC(void)
1559 {
1560 MS_U8 data = 0;
1561 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1562 _MBX_ReadReg(0x280F, &data);
1563 #else
1564 _MBX_ReadReg(0x28FD, &data);
1565 #endif
1566
1567 return data;
1568 }
1569
1570 #ifdef UTPA2
_HAL_INTERN_DTMB_ReadFrequencyOffset(MS_S16 * pFftfirstCfo,MS_S8 * pFftSecondCfo,MS_S16 * pSr)1571 static MS_BOOL _HAL_INTERN_DTMB_ReadFrequencyOffset(MS_S16 *pFftfirstCfo, MS_S8 *pFftSecondCfo, MS_S16 *pSr)
1572 #else
1573 static MS_S16 _HAL_INTERN_DTMB_ReadFrequencyOffset(void)
1574 #endif
1575 {
1576 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1577
1578 MS_U8 u8Data = 0;
1579 MS_S16 fftfirstCfo = 0;
1580 MS_S8 fftSecondCfo = 0;
1581 MS_S16 sr = 0;
1582
1583 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1584 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1585 {
1586 _MBX_ReadReg(0x3C4D, &u8Data);
1587 fftfirstCfo = u8Data;
1588 _MBX_ReadReg(0x3C4C, &u8Data);
1589 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1590
1591 _MBX_ReadReg(0x3C50, &u8Data);
1592 fftSecondCfo = u8Data;
1593 }
1594 else
1595 {
1596 _MBX_ReadReg(0x234D, &u8Data);
1597 fftfirstCfo = u8Data;
1598 _MBX_ReadReg(0x234C, &u8Data);
1599 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1600
1601 _MBX_ReadReg(0x2350, &u8Data);
1602 fftSecondCfo = u8Data;
1603 }
1604 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1605 _MBX_ReadReg(0x384D, &u8Data);
1606 fftfirstCfo = u8Data;
1607 _MBX_ReadReg(0x384C, &u8Data);
1608 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1609
1610 _MBX_ReadReg(0x3850, &u8Data);
1611 fftSecondCfo = u8Data;
1612 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1613 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1614 _MBX_ReadReg(0x124D, &u8Data);
1615 fftfirstCfo = u8Data;
1616 _MBX_ReadReg(0x124C, &u8Data);
1617 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1618 _MBX_ReadReg(0x1250, &u8Data);
1619 fftSecondCfo = u8Data;
1620 #else
1621 _MBX_ReadReg(0x3C4D, &u8Data);
1622 fftfirstCfo = u8Data;
1623 _MBX_ReadReg(0x3C4C, &u8Data);
1624 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1625
1626 _MBX_ReadReg(0x3C50, &u8Data);
1627 fftSecondCfo = u8Data;
1628 #endif
1629 #else
1630 _MBX_ReadReg(0x234D, &u8Data);
1631 fftfirstCfo = u8Data;
1632 _MBX_ReadReg(0x234C, &u8Data);
1633 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1634
1635 _MBX_ReadReg(0x2350, &u8Data);
1636 fftSecondCfo = u8Data;
1637 #endif
1638
1639 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1640 sr = 5670;
1641 else sr = 7560;
1642
1643 #ifdef UTPA2
1644 *pFftfirstCfo = fftfirstCfo;
1645 *pFftSecondCfo = fftSecondCfo;
1646 *pSr = sr;
1647
1648 return TRUE;
1649 #else
1650 return (MS_S16)((((double)fftfirstCfo/0x10000+(double)fftSecondCfo/0x20000))*(double)sr);
1651 #endif
1652 }
1653
_HAL_INTERN_DTMB_ReadSNRPercentage(void)1654 static MS_U8 _HAL_INTERN_DTMB_ReadSNRPercentage(void)
1655 {
1656 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1657
1658 MS_U8 data = 0;
1659 MS_U8 level = 0;
1660 MS_U32 snr = 0;
1661
1662 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1663 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1664 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1665 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1666 {
1667 if (!_HAL_INTERN_DTMB_FEC_Lock())
1668 level = 0;
1669 else
1670 {
1671 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1672 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1673 {
1674 _MBX_ReadReg(0x3BDA, &data);
1675 snr = data&0x3F;
1676 _MBX_ReadReg(0x3BD9, &data);
1677 snr = (snr<<8)|data;
1678 _MBX_ReadReg(0x3BD8, &data);
1679 snr = (snr<<8)|data;
1680 }
1681 else
1682 {
1683 _MBX_ReadReg(0x22DA, &data);
1684 snr = data&0x3F;
1685 _MBX_ReadReg(0x22D9, &data);
1686 snr = (snr<<8)|data;
1687 _MBX_ReadReg(0x22D8, &data);
1688 snr = (snr<<8)|data;
1689 }
1690 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1691 _MBX_ReadReg(0x37DA, &data);
1692 snr = data&0x3F;
1693 _MBX_ReadReg(0x37D9, &data);
1694 snr = (snr<<8)|data;
1695 _MBX_ReadReg(0x37D8, &data);
1696 snr = (snr<<8)|data;
1697 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1698 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1699 _MBX_ReadReg(0x11DA, &data);
1700 snr = data&0x3F;
1701 _MBX_ReadReg(0x11D9, &data);
1702 snr = (snr<<8)|data;
1703 _MBX_ReadReg(0x11D8, &data);
1704 snr = (snr<<8)|data;
1705 #else
1706 _MBX_ReadReg(0x3BDA, &data);
1707 snr = data&0x3F;
1708 _MBX_ReadReg(0x3BD9, &data);
1709 snr = (snr<<8)|data;
1710 _MBX_ReadReg(0x3BD8, &data);
1711 snr = (snr<<8)|data;
1712 #endif
1713 #else
1714 _MBX_ReadReg(0x22DA, &data);
1715 snr = data&0x3F;
1716 _MBX_ReadReg(0x22D9, &data);
1717 snr = (snr<<8)|data;
1718 _MBX_ReadReg(0x22D8, &data);
1719 snr = (snr<<8)|data;
1720 #endif
1721
1722 if (snr <= 4340 ) level = 1; // SNR <= 0.6 dB
1723 else if (snr <= 4983 ) level = 2; // SNR <= 1.2 dB
1724 else if (snr <= 5721 ) level = 3; // SNR <= 1.8 dB
1725 else if (snr <= 6569 ) level = 4; // SNR <= 2.4 dB
1726 else if (snr <= 7542 ) level = 5; // SNR <= 3.0 dB
1727 else if (snr <= 8659 ) level = 6; // SNR <= 3.6 dB
1728 else if (snr <= 9942 ) level = 7; // SNR <= 4.2 dB
1729 else if (snr <= 11415 ) level = 8; // SNR <= 4.8 dB
1730 else if (snr <= 13107 ) level = 9; // SNR <= 5.4 dB
1731 else if (snr <= 15048 ) level = 10; // SNR <= 6.0 dB
1732 else if (snr <= 17278 ) level = 11; // SNR <= 6.6 dB
1733 else if (snr <= 19838 ) level = 12; // SNR <= 7.2 dB
1734 else if (snr <= 22777 ) level = 13; // SNR <= 7.8 dB
1735 else if (snr <= 26151 ) level = 14; // SNR <= 8.4 dB
1736 else if (snr <= 30026 ) level = 15; // SNR <= 9.0 dB
1737 else if (snr <= 34474 ) level = 16; // SNR <= 9.6 dB
1738 else if (snr <= 39581 ) level = 17; // SNR <= 10.2 dB
1739 else if (snr <= 45446 ) level = 18; // SNR <= 10.8 dB
1740 else if (snr <= 52179 ) level = 19; // SNR <= 11.4 dB
1741 else if (snr <= 59909 ) level = 20; // SNR <= 12.0 dB
1742 else if (snr <= 68785 ) level = 21; // SNR <= 12.6 dB
1743 else if (snr <= 78975 ) level = 22; // SNR <= 13.2 dB
1744 else if (snr <= 90676 ) level = 23; // SNR <= 13.8 dB
1745 else if (snr <= 104110 ) level = 24; // SNR <= 14.4 dB
1746 else if (snr <= 119534 ) level = 25; // SNR <= 15.0 dB
1747 else if (snr <= 137244 ) level = 26; // SNR <= 15.6 dB
1748 else if (snr <= 157577 ) level = 27; // SNR <= 16.2 dB
1749 else if (snr <= 180922 ) level = 28; // SNR <= 16.8 dB
1750 else if (snr <= 207726 ) level = 29; // SNR <= 17.4 dB
1751 else if (snr <= 238502 ) level = 30; // SNR <= 18.0 dB
1752 else if (snr <= 273837 ) level = 31; // SNR <= 18.6 dB
1753 else if (snr <= 314407 ) level = 32; // SNR <= 19.2 dB
1754 else if (snr <= 360987 ) level = 33; // SNR <= 19.8 dB
1755 else if (snr <= 414469 ) level = 34; // SNR <= 20.4 dB
1756 else if (snr <= 475874 ) level = 35; // SNR <= 21.0 dB
1757 else if (snr <= 546376 ) level = 36; // SNR <= 21.6 dB
1758 else if (snr <= 627324 ) level = 37; // SNR <= 22.2 dB
1759 else if (snr <= 720264 ) level = 38; // SNR <= 22.8 dB
1760 else if (snr <= 826974 ) level = 39; // SNR <= 23.4 dB
1761 else if (snr <= 949493 ) level = 40; // SNR <= 24.0 dB
1762 else if (snr <= 1090164) level = 41; // SNR <= 24.6 dB
1763 else if (snr <= 1251676) level = 42; // SNR <= 25.2 dB
1764 else if (snr <= 1437116) level = 43; // SNR <= 25.8 dB
1765 else if (snr <= 1650030) level = 44; // SNR <= 26.4 dB
1766 else if (snr <= 1894488) level = 45; // SNR <= 27.0 dB
1767 else if (snr <= 2175163) level = 46; // SNR <= 27.6 dB
1768 else if (snr <= 2497421) level = 47; // SNR <= 28.2 dB
1769 else if (snr <= 2867423) level = 48; // SNR <= 28.8 dB
1770 else if (snr <= 3292242) level = 49; // SNR <= 29.4 dB
1771 else if (snr > 3292242) level = 50; // SNR <= 30.0 dB
1772 }
1773 }
1774 else
1775 {
1776 level = 0;
1777 }
1778
1779 return level*2;
1780 }
1781
1782 #ifdef UTPA2
_HAL_INTERN_DTMB_GetPreLdpcBer(MS_U32 * pBitErr,MS_U16 * pError_window)1783 static MS_BOOL _HAL_INTERN_DTMB_GetPreLdpcBer(MS_U32 *pBitErr, MS_U16 *pError_window)
1784 #else
1785 static MS_BOOL _HAL_INTERN_DTMB_GetPreLdpcBer(float *pber)
1786 #endif
1787 {
1788 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1789 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1790 #endif
1791
1792 MS_U8 u8Data=0;
1793 MS_U32 BitErr;
1794 MS_U16 error_window;
1795
1796 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1797 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1798 {
1799 _MBX_ReadReg(0x3F3B, &u8Data);
1800 BitErr = u8Data;
1801 _MBX_ReadReg(0x3F3A, &u8Data);
1802 BitErr = (BitErr << 8)|u8Data;
1803 _MBX_ReadReg(0x3F39, &u8Data);
1804 BitErr = (BitErr << 8)|u8Data;
1805 _MBX_ReadReg(0x3F38, &u8Data);
1806 BitErr = (BitErr << 8)|u8Data;
1807 }
1808 else
1809 {
1810 _MBX_ReadReg(0x263B, &u8Data);
1811 BitErr = u8Data;
1812 _MBX_ReadReg(0x263A, &u8Data);
1813 BitErr = (BitErr << 8)|u8Data;
1814 _MBX_ReadReg(0x2639, &u8Data);
1815 BitErr = (BitErr << 8)|u8Data;
1816 _MBX_ReadReg(0x2638, &u8Data);
1817 BitErr = (BitErr << 8)|u8Data;
1818 }
1819 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1820 _MBX_ReadReg(0x2D3B, &u8Data);
1821 BitErr = u8Data;
1822 _MBX_ReadReg(0x2D3A, &u8Data);
1823 BitErr = (BitErr << 8)|u8Data;
1824 _MBX_ReadReg(0x2D39, &u8Data);
1825 BitErr = (BitErr << 8)|u8Data;
1826 _MBX_ReadReg(0x2D38, &u8Data);
1827 BitErr = (BitErr << 8)|u8Data;
1828 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1829 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1830 _MBX_ReadReg(0x163B, &u8Data);
1831 BitErr = u8Data;
1832 _MBX_ReadReg(0x163A, &u8Data);
1833 BitErr = (BitErr << 8)|u8Data;
1834 _MBX_ReadReg(0x1639, &u8Data);
1835 BitErr = (BitErr << 8)|u8Data;
1836 _MBX_ReadReg(0x1638, &u8Data);
1837 BitErr = (BitErr << 8)|u8Data;
1838 #else
1839 _MBX_ReadReg(0x3F3B, &u8Data);
1840 BitErr = u8Data;
1841 _MBX_ReadReg(0x3F3A, &u8Data);
1842 BitErr = (BitErr << 8)|u8Data;
1843 _MBX_ReadReg(0x3F39, &u8Data);
1844 BitErr = (BitErr << 8)|u8Data;
1845 _MBX_ReadReg(0x3F38, &u8Data);
1846 BitErr = (BitErr << 8)|u8Data;
1847 #endif
1848 #else
1849 _MBX_ReadReg(0x263B, &u8Data);
1850 BitErr = u8Data;
1851 _MBX_ReadReg(0x263A, &u8Data);
1852 BitErr = (BitErr << 8)|u8Data;
1853 _MBX_ReadReg(0x2639, &u8Data);
1854 BitErr = (BitErr << 8)|u8Data;
1855 _MBX_ReadReg(0x2638, &u8Data);
1856 BitErr = (BitErr << 8)|u8Data;
1857 #endif
1858
1859 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1860 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1861 {
1862 _MBX_ReadReg(0x3F2F, &u8Data);
1863 error_window = u8Data;
1864 _MBX_ReadReg(0x3F2E, &u8Data);
1865 error_window = (error_window << 8)|u8Data;
1866 }
1867 else
1868 {
1869 _MBX_ReadReg(0x262F, &u8Data);
1870 error_window = u8Data;
1871 _MBX_ReadReg(0x262E, &u8Data);
1872 error_window = (error_window << 8)|u8Data;
1873 }
1874 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1875 _MBX_ReadReg(0x2D2F, &u8Data);
1876 error_window = u8Data;
1877 _MBX_ReadReg(0x2D2E, &u8Data);
1878 error_window = (error_window << 8)|u8Data;
1879 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1880 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1881 _MBX_ReadReg(0x162F, &u8Data);
1882 error_window = u8Data;
1883 _MBX_ReadReg(0x162E, &u8Data);
1884 error_window = (error_window << 8)|u8Data;
1885 #else
1886 _MBX_ReadReg(0x3F2F, &u8Data);
1887 error_window = u8Data;
1888 _MBX_ReadReg(0x3F2E, &u8Data);
1889 error_window = (error_window << 8)|u8Data;
1890 #endif
1891 #else
1892 _MBX_ReadReg(0x262F, &u8Data);
1893 error_window = u8Data;
1894 _MBX_ReadReg(0x262E, &u8Data);
1895 error_window = (error_window << 8)|u8Data;
1896 #endif
1897
1898 #ifdef UTPA2
1899 *pBitErr = BitErr;
1900 *pError_window = error_window;
1901 #else
1902 *pber=(float)BitErr/7488.0/(float)error_window;
1903 #endif
1904
1905 return TRUE;
1906 }
1907
_HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)1908 static MS_BOOL _HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
1909 {
1910 return _MBX_ReadReg(u16Addr, pu8Data);
1911 }
1912
_HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr,MS_U8 u8Data)1913 static MS_BOOL _HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
1914 {
1915 return _MBX_WriteReg(u16Addr, u8Data);
1916 }
1917
1918 //-------------------------------------------------------------------------------------------------
1919 // Global Functions
1920 //-------------------------------------------------------------------------------------------------
HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd,void * pArgs)1921 MS_BOOL HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd, void *pArgs)
1922 {
1923 MS_BOOL bResult = TRUE;
1924
1925 switch(eCmd)
1926 {
1927 case DMD_DTMB_HAL_CMD_Exit:
1928 bResult = _HAL_INTERN_DTMB_Exit();
1929 break;
1930 case DMD_DTMB_HAL_CMD_InitClk:
1931 _HAL_INTERN_DTMB_InitClk();
1932 break;
1933 case DMD_DTMB_HAL_CMD_Download:
1934 bResult = _HAL_INTERN_DTMB_Download();
1935 break;
1936 case DMD_DTMB_HAL_CMD_FWVERSION:
1937 _HAL_INTERN_DTMB_FWVERSION();
1938 break;
1939 case DMD_DTMB_HAL_CMD_SoftReset:
1940 bResult = _HAL_INTERN_DTMB_SoftReset();
1941 break;
1942 case DMD_DTMB_HAL_CMD_SetACICoef:
1943 bResult = _HAL_INTERN_DTMB_SetACICoef();
1944 break;
1945 case DMD_DTMB_HAL_CMD_SetDTMBMode:
1946 bResult = _HAL_INTERN_DTMB_SetDtmbMode();
1947 break;
1948 case DMD_DTMB_HAL_CMD_SetModeClean:
1949 bResult = _HAL_INTERN_DTMB_SetModeClean();
1950 break;
1951 case DMD_DTMB_HAL_CMD_Set_QAM_SR:
1952 bResult = _HAL_INTERN_DTMB_Set_QAM_SR();
1953 break;
1954 case DMD_DTMB_HAL_CMD_Active:
1955 break;
1956 case DMD_DTMB_HAL_CMD_AGCLock:
1957 bResult = _HAL_INTERN_DTMB_AGCLock();
1958 break;
1959 case DMD_DTMB_HAL_CMD_DTMB_PNP_Lock:
1960 bResult = _HAL_INTERN_DTMB_PNP_Lock();
1961 break;
1962 case DMD_DTMB_HAL_CMD_DTMB_FEC_Lock:
1963 bResult = _HAL_INTERN_DTMB_FEC_Lock();
1964 break;
1965 case DMD_DTMB_HAL_CMD_DVBC_PreLock:
1966 break;
1967 case DMD_DTMB_HAL_CMD_DVBC_Main_Lock:
1968 break;
1969 case DMD_DTMB_HAL_CMD_GetModulation:
1970 bResult = _HAL_INTERN_DTMB_GetModulation((DMD_DTMB_MODULATION_INFO *)pArgs);
1971 break;
1972 case DMD_DTMB_HAL_CMD_ReadIFAGC:
1973 *((MS_U16 *)pArgs) = _HAL_INTERN_DTMB_ReadIFAGC();
1974 break;
1975 case DMD_DTMB_HAL_CMD_ReadFrequencyOffset:
1976 #ifdef UTPA2
1977 bResult = _HAL_INTERN_DTMB_ReadFrequencyOffset(&((*((DMD_DTMB_CFO_DATA *)pArgs)).fftfirstCfo), &((*((DMD_DTMB_CFO_DATA *)pArgs)).fftSecondCfo), &((*((DMD_DTMB_CFO_DATA *)pArgs)).sr));
1978 #else
1979 *((MS_S16 *)pArgs) = _HAL_INTERN_DTMB_ReadFrequencyOffset();
1980 #endif
1981 break;
1982 case DMD_DTMB_HAL_CMD_ReadSNRPercentage:
1983 *((MS_U8 *)pArgs) = _HAL_INTERN_DTMB_ReadSNRPercentage();
1984 break;
1985 case DMD_DTMB_HAL_CMD_GetPreLdpcBer:
1986 #ifdef UTPA2
1987 bResult = _HAL_INTERN_DTMB_GetPreLdpcBer(&((*((DMD_DTMB_BER_DATA *)pArgs)).BitErr), &((*((DMD_DTMB_BER_DATA *)pArgs)).Error_window));
1988 #else
1989 bResult = _HAL_INTERN_DTMB_GetPreLdpcBer((float *)pArgs);
1990 #endif
1991 break;
1992 case DMD_DTMB_HAL_CMD_GetPreViterbiBer:
1993 break;
1994 case DMD_DTMB_HAL_CMD_GetPostViterbiBer:
1995 break;
1996 case DMD_DTMB_HAL_CMD_GetSNR:
1997 break;
1998 case DMD_DTMB_HAL_CMD_TS_INTERFACE_CONFIG:
1999 break;
2000 case DMD_DTMB_HAL_CMD_IIC_Bypass_Mode:
2001 break;
2002 case DMD_DTMB_HAL_CMD_SSPI_TO_GPIO:
2003 break;
2004 case DMD_DTMB_HAL_CMD_GPIO_GET_LEVEL:
2005 break;
2006 case DMD_DTMB_HAL_CMD_GPIO_SET_LEVEL:
2007 break;
2008 case DMD_DTMB_HAL_CMD_GPIO_OUT_ENABLE:
2009 break;
2010 case DMD_DTMB_HAL_CMD_DoIQSwap:
2011 break;
2012 case DMD_DTMB_HAL_CMD_GET_REG:
2013 bResult = _HAL_INTERN_DTMB_GetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, &((*((DMD_DTMB_REG_DATA *)pArgs)).u8Data));
2014 break;
2015 case DMD_DTMB_HAL_CMD_SET_REG:
2016 bResult = _HAL_INTERN_DTMB_SetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, (*((DMD_DTMB_REG_DATA *)pArgs)).u8Data);
2017 break;
2018 default:
2019 break;
2020 }
2021
2022 return bResult;
2023 }
2024
MDrv_DMD_DTMB_Initial_Hal_Interface(void)2025 MS_BOOL MDrv_DMD_DTMB_Initial_Hal_Interface(void)
2026 {
2027 return TRUE;
2028 }
2029
2030