308     while (RIU_ReadByte(MBRegBase + 0x00)) // wait VDMCU ready  in HAL_SYS_DMD_VD_MBX_DVB_WaitReady()
322     while(RIU_ReadByte(MBRegBase + 0x00) != 0xFF)           // wait MB_CNTL set done  in HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake()
336     RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8));   // ADDR_H  in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
337     RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr);          // ADDR_L  in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
338     RIU_WriteByte(MBRegBase + 0x00, 0x01);                 // MB_CNTL set read mode  in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
345     *u8Value = RIU_ReadByte(MBRegBase + 0x03);             // REG_DATA get  in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
346     RIU_WriteByte(MBRegBase + 0x00, 0x00);                 // MB_CNTL clear  in HAL_SYS_DMD_VD_MBX_DVB_ReadByte()
355     RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8));   // ADDR_H  in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
356     RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr);          // ADDR_L  in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
357     RIU_WriteByte(MBRegBase + 0x03, u8Data);               // REG_DATA  in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
358     RIU_WriteByte(MBRegBase + 0x00, 0x02);                 // MB_CNTL set write mode  in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
365     RIU_WriteByte(MBRegBase + 0x00, 0x00);                 // MB_CNTL clear  in HAL_SYS_DMD_VD_MBX_DVB_WriteByte()
373     RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8));    // ADDR_H  in HAL_SYS_DMD_VD_MBX_DVB_ReadDspReg()
374     RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr);           // ADDR_L  in HAL_SYS_DMD_VD_MBX_DVB_ReadDspReg()
375     RIU_WriteByte(MBRegBase + 0x00, 0x03);                  // MB_CNTL set read mode  in HAL_SYS_DMD_VD_MBX_DVB_ReadDspReg()
382     *u8Value = RIU_ReadByte(MBRegBase + 0x03);              // REG_DATA get  in HAL_SYS_DMD_VD_MBX_DVB_ReadDspReg()
383     RIU_WriteByte(MBRegBase + 0x00, 0x00);                  // MB_CNTL clear  in HAL_SYS_DMD_VD_MBX_DVB_ReadDspReg()
393     RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8));        // ADDR_H  in HAL_SYS_DMD_VD_MBX_DVB_WriteDspReg()
394     RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr);               // ADDR_L  in HAL_SYS_DMD_VD_MBX_DVB_WriteDspReg()
395     RIU_WriteByte(MBRegBase + 0x03, u8Value);                    // REG_DATA  in HAL_SYS_DMD_VD_MBX_DVB_WriteDspReg()
396     RIU_WriteByte(MBRegBase + 0x00, 0x04);                      // MB_CNTL set write mode  in HAL_SYS_DMD_VD_MBX_DVB_WriteDspReg()
403     RIU_WriteByte(MBRegBase + 0x00, 0x00);                      // MB_CNTL clear  in HAL_SYS_DMD_VD_MBX_DVB_WriteDspReg()
412     RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8));   // ADDR_H  in HAL_SYS_DMD_VD_MBX_DVB_DBG_ReadReg()
413     RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr);          // ADDR_L  in HAL_SYS_DMD_VD_MBX_DVB_DBG_ReadReg()
414     RIU_WriteByte(MBRegBase + 0x00, 0x05);                 // MB_CNTL set read mode  in HAL_SYS_DMD_VD_MBX_DVB_DBG_ReadReg()
421     *u8Value = RIU_ReadByte(MBRegBase + 0x03);             // REG_DATA get  in HAL_SYS_DMD_VD_MBX_DVB_DBG_ReadReg()
422     RIU_WriteByte(MBRegBase + 0x00, 0x00);                 // MB_CNTL clear  in HAL_SYS_DMD_VD_MBX_DVB_DBG_ReadReg()
432     RIU_WriteByte(MBRegBase + 0x02, (MS_U8)(u16Addr >> 8));   // ADDR_H  in HAL_SYS_DMD_VD_MBX_DVB_DBG_WriteReg()
433     RIU_WriteByte(MBRegBase + 0x01, (MS_U8)u16Addr);          // ADDR_L  in HAL_SYS_DMD_VD_MBX_DVB_DBG_WriteReg()
434     RIU_WriteByte(MBRegBase + 0x03, u8Data);               // REG_DATA  in HAL_SYS_DMD_VD_MBX_DVB_DBG_WriteReg()
435     RIU_WriteByte(MBRegBase + 0x00, 0x06);                 // MB_CNTL set write mode  in HAL_SYS_DMD_VD_MBX_DVB_DBG_WriteReg()
442     RIU_WriteByte(MBRegBase + 0x00, 0x00);                 // MB_CNTL clear  in HAL_SYS_DMD_VD_MBX_DVB_DBG_WriteReg()
453     RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));  in HAL_SYS_DMD_VD_MBX_ATSC_WriteByte()
454     RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));  in HAL_SYS_DMD_VD_MBX_ATSC_WriteByte()
455     RIU_WriteByte(MBRegBase + 0x10, u8Data);  in HAL_SYS_DMD_VD_MBX_ATSC_WriteByte()
456     RIU_WriteByte(MBRegBase + 0x1E, 0x01);  in HAL_SYS_DMD_VD_MBX_ATSC_WriteByte()
463         u8CheckFlag = RIU_ReadByte(MBRegBase + 0x1E);  in HAL_SYS_DMD_VD_MBX_ATSC_WriteByte()
476     RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));  in HAL_SYS_DMD_VD_MBX_ATSC_ReadByte()
477     RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));  in HAL_SYS_DMD_VD_MBX_ATSC_ReadByte()
478     RIU_WriteByte(MBRegBase + 0x1E, 0x02);  in HAL_SYS_DMD_VD_MBX_ATSC_ReadByte()
485         u8CheckFlag = RIU_ReadByte(MBRegBase + 0x1E);  in HAL_SYS_DMD_VD_MBX_ATSC_ReadByte()
488             u8Value = RIU_ReadByte(MBRegBase + 0x10);  in HAL_SYS_DMD_VD_MBX_ATSC_ReadByte()