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Searched refs:DVBT_FS (Results 1 – 15 of 15) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBT.c255 #define DVBT_FS 24000 // 24000 macro
258 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
259 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ¿ÀÈÄ 10:22:29 0x9E
1147 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1148 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBT.c253 #define DVBT_FS 48000 macro
256 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
257 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
1197 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1198 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT.c254 #define DVBT_FS 24000 // 24000 macro
257 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
258 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
1155 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1156 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_DVBT.c253 #define DVBT_FS 45474 // 24000 macro
256 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
257 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
1546 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1547 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBT.c256 #define DVBT_FS 45474 // 24000 macro
259 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
260 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ¿ÀÈÄ 10:22:29 0x9E
1321 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1322 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBT.c256 #define DVBT_FS 45474 // 24000 macro
259 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
260 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
1342 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1343 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBT.c255 #define DVBT_FS 45474 // 24000 macro
258 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
259 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
1560 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1561 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBT.c256 #define DVBT_FS 45474 // 24000 macro
259 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
260 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ¿ÀÈÄ 10:22:29 0x9E
1321 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1322 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBT.c256 #define DVBT_FS 45474 // 24000 macro
259 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
260 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ¿ÀÈÄ 10:22:29 0x9E
1321 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1322 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_DVBT.c254 #define DVBT_FS 45474 // 24000 macro
257 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
258 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
1544 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1545 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBT.c256 #define DVBT_FS 45474 // 24000 macro
259 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
260 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ¿ÀÈÄ 10:22:29 0x9E
1321 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1322 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBT.c256 #define DVBT_FS 45474 // 24000 macro
259 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
260 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ¿ÀÈÄ 10:22:29 0x9E
1321 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1322 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBT.c256 #define DVBT_FS 45474 // 24000 macro
259 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
260 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ¿ÀÈÄ 10:22:29 0x9E
1321 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1322 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBT.c256 #define DVBT_FS 45474 // 24000 macro
259 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
260 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
1342 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1343 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_DVBT.c254 #define DVBT_FS 45474 // 24000 macro
257 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
258 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
1555 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff); in INTERN_DVBT_Config()
1556 …status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xf… in INTERN_DVBT_Config()