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Searched refs:CKG_ODCLK_MASK (Results 1 – 25 of 58) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.c2700 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
2711 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
2721 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // [4..3] LPLL clock… in MHal_PNL_Init_XC_Clk()
2731 … W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h252 #define CKG_ODCLK_MASK (BIT(3) | BIT(4)) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.c2700 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
2711 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
2721 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // [4..3] LPLL clock… in MHal_PNL_Init_XC_Clk()
2731 … W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A DhalPNL.h218 #define CKG_ODCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.h213 #define CKG_ODCLK_MASK (BIT(5) | BIT(4) | BIT(3) | BIT(2)) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.h213 #define CKG_ODCLK_MASK (BIT(5) | BIT(4) | BIT(3) | BIT(2)) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A DhalPNL.h218 #define CKG_ODCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A DhalPNL.h218 #define CKG_ODCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A DhalPNL.h218 #define CKG_ODCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.c3473 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
3503 … W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div in MHal_PNL_Init_XC_Clk()
3534 … W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div in MHal_PNL_Init_XC_Clk()
3620 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL cl… in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h254 #define CKG_ODCLK_MASK (BIT(3) | BIT(4)) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.c3500 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
3530 … W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div in MHal_PNL_Init_XC_Clk()
3561 … W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div in MHal_PNL_Init_XC_Clk()
3647 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL cl… in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h254 #define CKG_ODCLK_MASK (BIT(3) | BIT(4)) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/
H A DregCLKGEN.h353 #define CKG_ODCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/
H A DregCLKGEN.h353 #define CKG_ODCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/
H A DregCLKGEN.h353 #define CKG_ODCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/
H A DregCLKGEN.h353 #define CKG_ODCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/
H A DregCLKGEN.h353 #define CKG_ODCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/
H A DregCLKGEN.h353 #define CKG_ODCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.h226 #define CKG_ODCLK_MASK (BIT(3) | BIT(2)) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/
H A DregCLKGEN.h353 #define CKG_ODCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/M7821/pws/
H A DregCLKGEN.h353 #define CKG_ODCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.h223 #define CKG_ODCLK_MASK (BIT(3) | BIT(2)) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mainz/pws/
H A DregCLKGEN.h353 #define CKG_ODCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mustang/pws/
H A DregCLKGEN.h353 #define CKG_ODCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro

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