Home
last modified time | relevance | path

Searched refs:CHANNEL0_IF6_CONFIG2 (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DhalTSO.c445 reg16 = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
896 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
923 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1237 reg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_ChIf_Cfg()
1284 pReg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h397 REG16_TSO CHANNEL0_IF6_CONFIG2; //1a member
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DhalTSO.c445 reg16 = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
896 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
923 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1237 reg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_ChIf_Cfg()
1284 pReg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h397 REG16_TSO CHANNEL0_IF6_CONFIG2; //1a member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DhalTSO.c445 reg16 = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
899 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
926 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1269 reg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_ChIf_Cfg()
1316 pReg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h397 REG16_TSO CHANNEL0_IF6_CONFIG2; //1a member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DhalTSO.c443 reg16 = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
905 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
932 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1275 reg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_ChIf_Cfg()
1322 pReg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h410 REG16_TSO CHANNEL0_IF6_CONFIG2; //1a member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DhalTSO.c446 reg16 = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_GetInputTSIF_Status()
908 … _REG16_SET(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
935 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1278 reg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_ChIf_Cfg()
1325 pReg = &(_TSOCtrl->CHANNEL0_IF6_CONFIG2); in HAL_TSO_Get_ChIf_Cfg()
H A DregTSO.h414 REG16_TSO CHANNEL0_IF6_CONFIG2; //1a member