| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | tegra210-p2371-2180.dts | 42 nvidia,lanes = "otg-1", "otg-2";
48 nvidia,lanes = "pcie-5", "pcie-6";
54 nvidia,lanes = "pcie-0";
60 nvidia,lanes = "pcie-1", "pcie-2",
67 nvidia,lanes = "sata-0";
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| H A D | tegra186-p2771-0000-500.dts | 19 nvidia,num-lanes = <4>;
24 nvidia,num-lanes = <0>;
29 nvidia,num-lanes = <1>;
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| H A D | tegra186-p2771-0000-000.dts | 19 nvidia,num-lanes = <2>;
24 nvidia,num-lanes = <1>;
29 nvidia,num-lanes = <1>;
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| H A D | fsl-ls2080a.dtsi | 102 num-lanes = <4>;
117 num-lanes = <4>;
132 num-lanes = <8>;
147 num-lanes = <4>;
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| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | dw-dp.c | 198 unsigned int lanes; member
441 unsigned int lanes, unsigned int rate) in dw_dp_bandwidth_ok() argument
446 max_bw = lanes * rate; in dw_dp_bandwidth_ok()
513 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) in dw_dp_phy_xmit_enable() argument
517 switch (lanes) { in dw_dp_phy_xmit_enable()
521 xmit_enable = GENMASK(lanes - 1, 0); in dw_dp_phy_xmit_enable()
579 link->lanes = min_t(u8, dp->phy.attrs.bus_width, in dw_dp_link_probe()
597 unsigned int lanes = link->lanes, *vs, *pe; in dw_dp_link_train_update_vs_emph() local
604 for (i = 0; i < lanes; i++) { in dw_dp_link_train_update_vs_emph()
608 phy_cfg.dp.lanes = lanes; in dw_dp_link_train_update_vs_emph()
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| H A D | dw_mipi_dsi2.c | 264 unsigned char lanes; member
290 u32 lanes; member
350 int bpp, lanes; in dw_mipi_dsi2_get_lane_rate() local
371 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; in dw_mipi_dsi2_get_lane_rate()
373 do_div(tmp, lanes); in dw_mipi_dsi2_get_lane_rate()
870 dsi2->lanes /= 2; in dw_mipi_dsi2_connector_init()
873 dsi2->slave->lanes = dsi2->lanes; in dw_mipi_dsi2_connector_init()
1009 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); in dw_mipi_dsi2_phy_mode_cfg()
1212 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); in dw_mipi_dsi2_connector_prepare()
1409 if (device->lanes < 1 || device->lanes > 8) in dw_mipi_dsi2_host_attach()
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| H A D | dw_mipi_dsi.c | 244 u32 lanes; member
553 int bpp, lanes; in dw_mipi_dsi_get_lane_rate() local
565 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes; in dw_mipi_dsi_get_lane_rate()
567 do_div(tmp, lanes); in dw_mipi_dsi_get_lane_rate()
1081 N_LANES(dsi->lanes)); in dw_mipi_dsi_dphy_interface_config()
1149 dsi->lanes /= 2; in dw_mipi_dsi_connector_init()
1150 dsi->slave->lanes = dsi->lanes; in dw_mipi_dsi_connector_init()
1242 grf_field_write(dsi, ENABLE_N, map[dsi->lanes]); in mipi_dphy_init()
1294 dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes); in dw_mipi_dsi_connector_prepare()
1670 if (device->lanes < 1 || device->lanes > 8) in dw_mipi_dsi_host_attach()
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| H A D | rk618_dsi.c | 223 unsigned int lanes; member
307 unsigned int lanes = dsi->lanes; in rk618_dsi_set_hs_clk() local
311 do_div(bandwidth, lanes); in rk618_dsi_set_hs_clk()
407 LANE_EN_CK | GENMASK(dsi->lanes - 1 + 2, 2)); in rk618_dsi_phy_power_on()
644 value = N_LANES(dsi->lanes - 1) | PHY_STOP_WAIT_TIME(0x20); in rk618_dsi_pre_enable()
693 dsi->phy.rate / USEC_PER_SEC, dsi->lanes); in rk618_dsi_enable()
992 if (device->lanes < 1 || device->lanes > 4) in rk618_dsi_host_attach()
995 dsi->lanes = device->lanes; in rk618_dsi_host_attach()
1029 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); in rk618_dsi_child_post_bind()
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| /rk3399_rockchip-uboot/drivers/video/ |
| H A D | anx9804.h | 20 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp);
22 static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, in anx9804_init() argument
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| H A D | anx9804.c | 29 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) in anx9804_init() argument
106 i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes); in anx9804_init()
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| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | ls1012a_serdes.c | 13 u8 lanes[SRDS_MAX_LANES]; member
43 return ptr->lanes[lane]; in serdes_get_prtcl()
69 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
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| H A D | ls1043a_serdes.c | 13 u8 lanes[SRDS_MAX_LANES]; member
55 return ptr->lanes[lane]; in serdes_get_prtcl()
81 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
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| H A D | ls1046a_serdes.c | 13 u8 lanes[SRDS_MAX_LANES]; member
68 return ptr->lanes[lane]; in serdes_get_prtcl()
94 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
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| H A D | ls2080a_serdes.c | 12 u8 lanes[SRDS_MAX_LANES]; member
93 return ptr->lanes[lane]; in serdes_get_prtcl()
119 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
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| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/ |
| H A D | c29x_serdes.c | 19 u8 lanes[SRDS1_MAX_LANES]; member
65 enum srds_prtcl lane_prtcl = ptr->lanes[lane]; in fsl_serdes_init()
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| H A D | fsl_corenet_serdes.c | 64 } lanes[SRDS_MAX_LANES] = { variable
98 return lanes[lane].idx; in serdes_get_lane_idx()
103 return lanes[lane].bank; in serdes_get_bank_by_lane()
111 int bank = lanes[lane].bank; in serdes_lane_enabled()
112 int word = lanes[lane].lpd / 32; in serdes_lane_enabled()
113 int bit = lanes[lane].lpd % 32; in serdes_lane_enabled()
670 if (lanes[lane].bank == bank) in fsl_serdes_init()
672 idx = lanes[lane].idx; in fsl_serdes_init()
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| H A D | t2080_serdes.c | 16 u8 lanes[SRDS_MAX_LANES]; member
199 return ptr->lanes[lane]; in serdes_get_prtcl()
224 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
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| /rk3399_rockchip-uboot/include/ |
| H A D | generic-phy-dp.h | 36 unsigned int lanes; member
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| H A D | generic-phy-mipi-dphy.h | 274 unsigned char lanes; member
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| /rk3399_rockchip-uboot/drivers/pci/ |
| H A D | pci_tegra.c | 384 static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes, in tegra_pcie_get_xbar_config() argument
389 switch (lanes) { in tegra_pcie_get_xbar_config()
402 switch (lanes) { in tegra_pcie_get_xbar_config()
421 switch (lanes) { in tegra_pcie_get_xbar_config()
434 switch (lanes) { in tegra_pcie_get_xbar_config()
458 static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes) in tegra_pcie_parse_port_info() argument
469 *lanes = err; in tegra_pcie_parse_port_info()
491 u32 lanes = 0; in tegra_pcie_parse_dt() local
539 lanes |= num_lanes << (index << 3); in tegra_pcie_parse_dt()
562 err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id, in tegra_pcie_parse_dt()
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| H A D | Kconfig | 62 Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
63 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports
64 with a total of 5 lanes. Some boards require this for Ethernet
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| /rk3399_rockchip-uboot/drivers/video/drm/rk628/ |
| H A D | rk628_gvi.c | 30 rk628->gvi.lanes = val; in rk628_gvi_parse()
116 do_div(total_bw, gvi->lanes); in rk628_gvi_get_lane_rate()
139 SYS_CTRL0_LANE_NUM(gvi->lanes - 1)); in rk628_gvi_pre_enable()
265 rate, gvi->lanes, gvi->byte_mode, gvi->color_depth, in rk628_gvi_enable()
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| /rk3399_rockchip-uboot/drivers/video/bridge/ |
| H A D | anx6345.c | 355 u8 colordepth, lanes, data_rate, c; in anx6345_enable() local
377 if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) { in anx6345_enable()
381 lanes &= DP_MAX_LANE_COUNT_MASK; in anx6345_enable()
382 debug("%s: lanes: %d\n", __func__, (int)lanes); in anx6345_enable()
386 anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes); in anx6345_enable()
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| /rk3399_rockchip-uboot/drivers/phy/ |
| H A D | phy-rockchip-naneng-edp.c | 155 for (lane = 0; lane < dp->lanes; lane++) in rockchip_edp_phy_set_voltages()
226 FIELD_PREP(EDP_PHY_TX_PD, ~GENMASK(dp->lanes - 1, 0))); in rockchip_edp_phy_set_rate()
237 FIELD_PREP(EDP_PHY_TX_IDLE, ~GENMASK(dp->lanes - 1, 0))); in rockchip_edp_phy_set_rate()
260 switch (dp->lanes) { in rockchip_edp_phy_verify_config()
276 for (i = 0; i < dp->lanes; i++) { in rockchip_edp_phy_verify_config()
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| /rk3399_rockchip-uboot/drivers/phy/marvell/ |
| H A D | Kconfig | 7 This driver passes over the lanes
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