| /rk3399_ARM-atf/plat/nxp/common/psci/ |
| H A D | plat_psci.c | 175 if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend()
183 } else if (state->pwr_domain_state[PLAT_MAX_LVL] in _pwr_suspend()
194 else if (state->pwr_domain_state[PLAT_CLSTR_LVL] == in _pwr_suspend()
205 else if (state->pwr_domain_state[PLAT_CLSTR_LVL] == in _pwr_suspend()
216 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend()
227 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) { in _pwr_suspend()
248 if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend_finish()
258 } else if (state->pwr_domain_state[PLAT_MAX_LVL] in _pwr_suspend_finish()
271 else if (state->pwr_domain_state[PLAT_CLSTR_LVL] == in _pwr_suspend_finish()
284 else if (state->pwr_domain_state[PLAT_CLSTR_LVL] == in _pwr_suspend_finish()
[all …]
|
| /rk3399_ARM-atf/plat/arm/board/fvp/ |
| H A D | fvp_pm.c | 78 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_power_domain_on_finish_common()
85 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == in fvp_power_domain_on_finish_common()
102 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == in fvp_power_domain_on_finish_common()
174 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_pwr_domain_off()
186 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == in fvp_pwr_domain_off()
204 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_pwr_domain_suspend()
208 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_pwr_domain_suspend()
224 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == in fvp_pwr_domain_suspend()
229 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == in fvp_pwr_domain_suspend()
273 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_pwr_domain_suspend_finish()
[all …]
|
| /rk3399_ARM-atf/plat/imx/common/ |
| H A D | imx8_psci.c | 43 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
45 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE; in imx_validate_power_state()
47 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
59 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in imx_get_sys_suspend_power_state()
60 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/xilinx/zynqmp/ |
| H A D | plat_psci.c | 82 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_off()
112 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_suspend()
115 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? in zynqmp_pwr_domain_suspend()
123 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in zynqmp_pwr_domain_suspend()
133 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_on_finish()
150 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_suspend_finish()
159 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in zynqmp_pwr_domain_suspend_finish()
225 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in zynqmp_validate_power_state()
227 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in zynqmp_validate_power_state()
239 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
[all …]
|
| /rk3399_ARM-atf/plat/xilinx/versal/ |
| H A D | plat_psci.c | 80 __func__, i, target_state->pwr_domain_state[i]); in versal_pwr_domain_suspend()
85 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend()
89 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? in versal_pwr_domain_suspend()
97 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend()
121 __func__, i, target_state->pwr_domain_state[i]); in versal_pwr_domain_suspend_finish()
131 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend_finish()
238 __func__, i, target_state->pwr_domain_state[i]); in versal_pwr_domain_off()
287 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_validate_power_state()
289 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_validate_power_state()
307 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
[all …]
|
| /rk3399_ARM-atf/plat/rockchip/common/ |
| H A D | plat_pm.c | 22 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
24 ((state)->pwr_domain_state[MPIDR_AFFLVL1])
26 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
151 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in rockchip_validate_power_state()
155 req_state->pwr_domain_state[i] = in rockchip_validate_power_state()
159 req_state->pwr_domain_state[i] = in rockchip_validate_power_state()
175 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rockchip_get_sys_suspend_power_state()
230 lvl_state = target_state->pwr_domain_state[lvl]; in rockchip_pwr_domain_off()
266 lvl_state = target_state->pwr_domain_state[lvl]; in rockchip_pwr_domain_suspend()
287 lvl_state = target_state->pwr_domain_state[lvl]; in rockchip_pwr_domain_on_finish()
[all …]
|
| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t210/ |
| H A D | plat_psci_handlers.c | 55 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; in tegra_soc_validate_power_state()
64 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; in tegra_soc_validate_power_state()
65 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; in tegra_soc_validate_power_state()
82 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in tegra_soc_validate_power_state()
84 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = in tegra_soc_validate_power_state()
197 const plat_local_state_t *pwr_domain_state = in tegra_soc_pwr_domain_suspend() local
198 target_state->pwr_domain_state; in tegra_soc_pwr_domain_suspend()
199 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; in tegra_soc_pwr_domain_suspend()
200 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; in tegra_soc_pwr_domain_suspend()
201 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; in tegra_soc_pwr_domain_suspend()
[all …]
|
| /rk3399_ARM-atf/plat/qti/common/src/ |
| H A D | qti_pm.c | 115 req_state->pwr_domain_state[i] = state_id & in qti_validate_power_state()
159 if ((target_state->pwr_domain_state[QTI_PWR_LVL0] == in is_cpu_off()
161 (target_state->pwr_domain_state[QTI_PWR_LVL0] == in is_cpu_off()
172 (const uint8_t *)target_state->pwr_domain_state; in qti_cpu_power_on_finish()
187 target_state->pwr_domain_state); in qti_node_power_off()
197 pwr_domain_state); in qti_node_suspend()
207 (const uint8_t *)target_state->pwr_domain_state; in qti_node_suspend_finish()
251 req_state->pwr_domain_state[i++] = in qti_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/renesas/rcar_gen4/ |
| H A D | plat_pm.c | 25 #define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
26 #define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1])
27 #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
169 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in rcar_validate_power_state()
172 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_validate_power_state()
188 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = in rcar_get_sys_suspend_power_state()
192 req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE; in rcar_get_sys_suspend_power_state()
195 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/xilinx/versal_net/ |
| H A D | plat_psci_pm.c | 77 __func__, i, target_state->pwr_domain_state[i]); in versal_net_pwr_domain_off()
223 __func__, i, target_state->pwr_domain_state[i]); in versal_net_pwr_domain_suspend()
226 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_net_pwr_domain_suspend()
230 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? in versal_net_pwr_domain_suspend()
265 __func__, i, target_state->pwr_domain_state[i]); in versal_net_pwr_domain_suspend_finish()
274 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_net_pwr_domain_suspend_finish()
320 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_net_validate_power_state()
322 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_net_validate_power_state()
344 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in versal_net_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/imx/imx8m/include/ |
| H A D | imx8m_psci.h | 10 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
11 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
12 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
|
| /rk3399_ARM-atf/plat/mediatek/mt8192/include/ |
| H A D | plat_pm.h | 28 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER])
30 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS])
32 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
|
| /rk3399_ARM-atf/plat/imx/imx9/common/include/ |
| H A D | imx9_psci_common.h | 14 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
15 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
16 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
|
| /rk3399_ARM-atf/plat/mediatek/mt8195/include/ |
| H A D | plat_pm.h | 28 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER])
30 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS])
32 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
|
| /rk3399_ARM-atf/plat/nuvoton/npcm845x/ |
| H A D | npcm845x_psci.c | 170 __func__, i, target_state->pwr_domain_state[i]); in npcm845x_pwr_domain_suspend()
190 __func__, i, target_state->pwr_domain_state[i]); in npcm845x_pwr_domain_on_finish()
193 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in npcm845x_pwr_domain_on_finish()
212 __func__, i, target_state->pwr_domain_state[i]); in npcm845x_pwr_domain_suspend_finish()
215 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in npcm845x_pwr_domain_suspend_finish()
285 req_state->pwr_domain_state[i++] = (uint8_t)state_id & in npcm845x_validate_power_state()
307 req_state->pwr_domain_state[i] = (uint8_t)PLAT_LOCAL_STATE_OFF; in npcm845x_get_sys_suspend_power_state()
369 __func__, i, target_state->pwr_domain_state[i]); in npcm845x_pwr_domain_off()
|
| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/ |
| H A D | plat_psci_handlers.c | 81 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; in tegra_soc_validate_power_state()
82 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; in tegra_soc_validate_power_state()
103 const plat_local_state_t *pwr_domain_state; in tegra_soc_pwr_domain_suspend() local
112 pwr_domain_state = target_state->pwr_domain_state; in tegra_soc_pwr_domain_suspend()
113 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & in tegra_soc_pwr_domain_suspend()
115 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & in tegra_soc_pwr_domain_suspend()
281 const plat_local_state_t *pwr_domain_state = in tegra_soc_pwr_domain_power_down_wfi() local
282 target_state->pwr_domain_state; in tegra_soc_pwr_domain_power_down_wfi()
284 uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & in tegra_soc_pwr_domain_power_down_wfi()
372 uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; in tegra_soc_pwr_domain_on_finish()
[all …]
|
| /rk3399_ARM-atf/plat/mediatek/mt8173/ |
| H A D | plat_pm.c | 37 #define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0]
38 #define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1]
40 (state)->pwr_domain_state[MTK_PWR_LVL2] : 0)
376 assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF); in plat_power_domain_on_finish()
379 (state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF)) in plat_power_domain_on_finish()
382 if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) { in plat_power_domain_on_finish()
388 (state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF)) in plat_power_domain_on_finish()
406 if (state->pwr_domain_state[MTK_PWR_LVL0] == MTK_LOCAL_STATE_RET) in plat_power_domain_suspend_finish()
439 req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; in plat_get_sys_suspend_power_state()
490 req_state->pwr_domain_state[MTK_PWR_LVL0] = in plat_validate_power_state()
[all …]
|
| /rk3399_ARM-atf/plat/amd/versal2/ |
| H A D | plat_psci_pm.c | 79 __func__, i, target_state->pwr_domain_state[i]); in versal2_pwr_domain_off()
170 __func__, i, target_state->pwr_domain_state[i]); in versal2_pwr_domain_suspend()
175 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal2_pwr_domain_suspend()
179 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? in versal2_pwr_domain_suspend()
252 __func__, i, target_state->pwr_domain_state[i]); in versal2_pwr_domain_suspend_finish()
259 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal2_pwr_domain_suspend_finish()
326 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal2_validate_power_state()
328 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal2_validate_power_state()
349 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in versal2_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/allwinner/common/ |
| H A D | sunxi_scpi_pm.c | 44 ((state)->pwr_domain_state[CPU_PWR_LVL])
46 ((state)->pwr_domain_state[CLUSTER_PWR_LVL])
48 ((state)->pwr_domain_state[SYSTEM_PWR_LVL])
168 req_state->pwr_domain_state[i] = local_pstate; in sunxi_validate_power_state()
174 req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN; in sunxi_validate_power_state()
185 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in sunxi_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/renesas/common/ |
| H A D | plat_pm.c | 38 #define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
39 #define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1])
40 #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
265 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in rcar_validate_power_state()
268 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_validate_power_state()
287 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_get_sys_suspend_power_state()
292 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSCI_LOCAL_STATE_RUN; in rcar_get_sys_suspend_power_state()
294 req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE; in rcar_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/include/plat/arm/css/common/ |
| H A D | css_pm.h | 19 #define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0]
20 #define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1]
25 return state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL]; in css_system_pwr_state()
|
| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/ |
| H A D | plat_psci_handlers.c | 82 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in tegra_soc_validate_power_state()
83 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN; in tegra_soc_validate_power_state()
116 const plat_local_state_t *pwr_domain_state; in tegra_soc_pwr_domain_suspend() local
131 pwr_domain_state = target_state->pwr_domain_state; in tegra_soc_pwr_domain_suspend()
132 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & in tegra_soc_pwr_domain_suspend()
265 const plat_local_state_t *pwr_domain_state = in tegra_soc_pwr_domain_power_down_wfi() local
266 target_state->pwr_domain_state; in tegra_soc_pwr_domain_power_down_wfi()
268 uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & in tegra_soc_pwr_domain_power_down_wfi()
348 uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; in tegra_soc_pwr_domain_on_finish()
|
| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hikey_pm.c | 24 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
26 ((state)->pwr_domain_state[MPIDR_AFFLVL1])
28 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
168 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in hikey_get_sys_suspend_power_state()
235 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey_validate_power_state()
239 req_state->pwr_domain_state[i] = in hikey_validate_power_state()
|
| /rk3399_ARM-atf/plat/intel/soc/common/ |
| H A D | socfpga_psci.c | 106 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_off()
129 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_suspend()
146 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_on_finish()
177 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_suspend_finish()
291 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
292 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
|
| /rk3399_ARM-atf/plat/amlogic/axg/ |
| H A D | axg_pm.c | 102 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in axg_pwr_domain_on_finish()
117 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in axg_pwr_domain_off()
124 if (target_state->pwr_domain_state[MPIDR_AFFLVL2] == in axg_pwr_domain_off()
128 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == in axg_pwr_domain_off()
|