1*4ddfb6f1SJacky Bai /* 2*4ddfb6f1SJacky Bai * Copyright 2025 NXP 3*4ddfb6f1SJacky Bai * 4*4ddfb6f1SJacky Bai * SPDX-License-Identifier: BSD-3-Clause 5*4ddfb6f1SJacky Bai */ 6*4ddfb6f1SJacky Bai 7*4ddfb6f1SJacky Bai #ifndef IMX9_PSCI_H 8*4ddfb6f1SJacky Bai #define IMX9_PSCI_H 9*4ddfb6f1SJacky Bai 10*4ddfb6f1SJacky Bai #include <lib/psci/psci.h> 11*4ddfb6f1SJacky Bai 12*4ddfb6f1SJacky Bai #include <platform_def.h> 13*4ddfb6f1SJacky Bai 14*4ddfb6f1SJacky Bai #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 15*4ddfb6f1SJacky Bai #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 16*4ddfb6f1SJacky Bai #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 17*4ddfb6f1SJacky Bai 18*4ddfb6f1SJacky Bai extern uintptr_t secure_entrypoint; 19*4ddfb6f1SJacky Bai extern uint32_t mask_all[IMR_NUM]; 20*4ddfb6f1SJacky Bai 21*4ddfb6f1SJacky Bai int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint); 22*4ddfb6f1SJacky Bai void imx_set_cpu_boot_entry(uint32_t core_id, uint64_t boot_entry, uint32_t flag); 23*4ddfb6f1SJacky Bai int imx_pwr_domain_on(u_register_t mpidr); 24*4ddfb6f1SJacky Bai void imx_pwr_domain_on_finish(const psci_power_state_t *target_state); 25*4ddfb6f1SJacky Bai void imx_pwr_domain_off(const psci_power_state_t *target_state); 26*4ddfb6f1SJacky Bai void imx_pwr_domain_suspend(const psci_power_state_t *target_state); 27*4ddfb6f1SJacky Bai void imx_pwr_domain_suspend_finish(const psci_power_state_t *target_state); 28*4ddfb6f1SJacky Bai void imx_pwr_domain_pwr_down(const psci_power_state_t *target_state); 29*4ddfb6f1SJacky Bai 30*4ddfb6f1SJacky Bai #endif /* IMX9_PSCI_H */ 31