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Searched refs:lvl (Results 1 – 20 of 20) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/common/
H A Dplat_pm.c51 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, in rockchip_soc_hlvl_pwr_dm_off() argument
72 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, in rockchip_soc_hlvl_pwr_dm_suspend() argument
78 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, in rockchip_soc_hlvl_pwr_dm_on_finish() argument
94 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, in rockchip_soc_hlvl_pwr_dm_resume() argument
216 uint32_t lvl; in rockchip_pwr_domain_off() local
229 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_off()
230 lvl_state = target_state->pwr_domain_state[lvl]; in rockchip_pwr_domain_off()
231 ret = rockchip_soc_hlvl_pwr_dm_off(lvl, lvl_state); in rockchip_pwr_domain_off()
243 uint32_t lvl; in rockchip_pwr_domain_suspend() local
265 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend()
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/rk3399_ARM-atf/lib/psci/
H A Dpsci_common.c179 unsigned int lvl; in psci_is_last_cpu_to_idle_at_pwrlvl() local
189 for (lvl = PSCI_CPU_PWR_LVL + U(1); lvl < end_pwrlvl; lvl++) { in psci_is_last_cpu_to_idle_at_pwrlvl()
363 unsigned int lvl; in psci_update_req_local_pwr_states() local
371 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= max_pwrlvl; lvl++) { in psci_update_req_local_pwr_states()
373 prev[lvl - 1U] = *psci_get_req_local_pwr_states(lvl, cpu_idx); in psci_update_req_local_pwr_states()
376 if (lvl <= end_pwrlvl) { in psci_update_req_local_pwr_states()
377 req_state = state_info->pwr_domain_state[lvl]; in psci_update_req_local_pwr_states()
381 psci_set_req_local_pwr_state(lvl, cpu_idx, req_state); in psci_update_req_local_pwr_states()
392 unsigned int lvl; in psci_restore_req_local_pwr_states() local
399 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= max_pwrlvl; lvl++) { in psci_restore_req_local_pwr_states()
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H A Dpsci_stat.c79 unsigned int lvl, parent_idx; in psci_stats_update_pwr_down() local
86 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_stats_update_pwr_down()
89 if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0) in psci_stats_update_pwr_down()
111 unsigned int lvl, parent_idx; in psci_stats_update_pwr_up() local
140 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_stats_update_pwr_up()
141 local_state = state_info->pwr_domain_state[lvl]; in psci_stats_update_pwr_up()
150 residency = plat_psci_stat_get_residency(lvl, state_info, in psci_stats_update_pwr_up()
157 stat_idx = get_stat_idx(local_state, lvl); in psci_stats_update_pwr_up()
177 unsigned int pwrlvl, lvl, parent_idx, target_idx, stat_idx; in psci_get_stat() local
209 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl < pwrlvl; lvl++) in psci_get_stat()
H A Dpsci_off.c26 unsigned int lvl; in psci_set_power_off_state() local
28 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in psci_set_power_off_state()
29 state_info->pwr_domain_state[lvl] = PLAT_MAX_OFF_STATE; in psci_set_power_off_state()
/rk3399_ARM-atf/drivers/arm/css/scp/
H A Dcss_pm_scmi.c117 static inline void css_scp_set_state_pwr_lvl(uint32_t *pwr_state, unsigned int lvl) in css_scp_set_state_pwr_lvl() argument
119 unsigned int max_lvl = (lvl == 0U) ? 0U : (lvl - 1U); in css_scp_set_state_pwr_lvl()
150 unsigned int lvl, channel_id, domain_id; in css_scp_suspend() local
162 for (lvl = ARM_PWR_LVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in css_scp_suspend()
163 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) in css_scp_suspend()
166 assert(target_state->pwr_domain_state[lvl] == in css_scp_suspend()
172 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, in css_scp_suspend()
176 css_scp_set_state_pwr_lvl(&scmi_pwr_state, lvl); in css_scp_suspend()
197 unsigned int lvl = 0, channel_id, domain_id; in css_scp_off() local
208 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in css_scp_off()
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/rk3399_ARM-atf/plat/socionext/synquacer/drivers/scp/
H A Dsq_scmi.c102 int lvl = 0, ret; in sq_scmi_off() local
109 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in sq_scmi_off()
110 if (target_state->pwr_domain_state[lvl] == SQ_LOCAL_STATE_RUN) in sq_scmi_off()
113 assert(target_state->pwr_domain_state[lvl] == in sq_scmi_off()
115 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, in sq_scmi_off()
119 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); in sq_scmi_off()
138 int lvl = 0, ret, core_pos; in sq_scmi_on() local
141 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) in sq_scmi_on()
142 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, in sq_scmi_on()
145 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); in sq_scmi_on()
/rk3399_ARM-atf/plat/common/
H A Dplat_psci_common.c99 u_register_t plat_psci_stat_get_residency(unsigned int lvl, in plat_psci_stat_get_residency() argument
106 assert((lvl >= PSCI_CPU_PWR_LVL) && (lvl <= PLAT_MAX_PWR_LVL)); in plat_psci_stat_get_residency()
109 if (lvl == PSCI_CPU_PWR_LVL) in plat_psci_stat_get_residency()
161 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, in plat_get_target_pwr_state() argument
165 (void)lvl; in plat_get_target_pwr_state()
/rk3399_ARM-atf/plat/rockchip/common/include/
H A Dplat_private.h115 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
120 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
122 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
127 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
/rk3399_ARM-atf/plat/renesas/rcar_gen5/
H A Dplat_pm_scmi.c122 unsigned int lvl = 0, channel_id, domain_id; in rcar_scmi_cpuoff() local
133 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rcar_scmi_cpuoff()
134 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) in rcar_scmi_cpuoff()
137 assert(target_state->pwr_domain_state[lvl] == in rcar_scmi_cpuoff()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t210/
H A Dplat_psci_handlers.c101 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, in tegra_soc_get_target_pwr_state() argument
112 if (lvl == MPIDR_AFFLVL1) in tegra_soc_get_target_pwr_state()
114 if (lvl == MPIDR_AFFLVL2) in tegra_soc_get_target_pwr_state()
117 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { in tegra_soc_get_target_pwr_state()
175 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && in tegra_soc_get_target_pwr_state()
/rk3399_ARM-atf/plat/nvidia/tegra/common/
H A Dtegra_pm.c335 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, in plat_get_target_pwr_state() argument
339 return tegra_soc_get_target_pwr_state(lvl, states, ncpu); in plat_get_target_pwr_state()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/
H A Dplat_psci_handlers.c257 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, in tegra_soc_get_target_pwr_state() argument
265 if ((lvl == (uint32_t)MPIDR_AFFLVL2) && in tegra_soc_get_target_pwr_state()
271 if (lvl == (uint32_t)MPIDR_AFFLVL1) { in tegra_soc_get_target_pwr_state()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_psci_handlers.c242 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, in tegra_soc_get_target_pwr_state() argument
250 if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) { in tegra_soc_get_target_pwr_state()
255 if (lvl == (uint32_t)MPIDR_AFFLVL1) { in tegra_soc_get_target_pwr_state()
/rk3399_ARM-atf/plat/nvidia/tegra/include/
H A Dtegra_private.h122 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
/rk3399_ARM-atf/plat/nxp/common/psci/
H A Dplat_psci.c343 int lvl = (pwr_state & PWR_STATE_LVL_MASK); in _pwr_state_validate() local
345 switch (lvl) { in _pwr_state_validate()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dpmu.c670 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, in rockchip_soc_hlvl_pwr_dm_off() argument
673 if (lvl == MPIDR_AFFLVL1) { in rockchip_soc_hlvl_pwr_dm_off()
695 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state) in rockchip_soc_hlvl_pwr_dm_suspend() argument
697 if (lvl == MPIDR_AFFLVL1) { in rockchip_soc_hlvl_pwr_dm_suspend()
713 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, in rockchip_soc_hlvl_pwr_dm_on_finish() argument
716 if (lvl == MPIDR_AFFLVL1) { in rockchip_soc_hlvl_pwr_dm_on_finish()
733 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state) in rockchip_soc_hlvl_pwr_dm_resume() argument
735 if (lvl == MPIDR_AFFLVL1) { in rockchip_soc_hlvl_pwr_dm_resume()
/rk3399_ARM-atf/include/plat/common/
H A Dplatform.h390 u_register_t plat_psci_stat_get_residency(unsigned int lvl,
393 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
/rk3399_ARM-atf/fdts/
H A Dfvp-base-psci-common.dtsi37 max-pwr-lvl = <2>;
/rk3399_ARM-atf/plat/mediatek/mt8173/
H A Dplat_pm.c588 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, in plat_get_target_pwr_state() argument
/rk3399_ARM-atf/docs/
H A Dporting-guide.rst2967 identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2986 power domain level ``lvl`` (first argument) within the power domain. The function