51 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,  in rockchip_soc_hlvl_pwr_dm_off()  argument
72 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,  in rockchip_soc_hlvl_pwr_dm_suspend()  argument
78 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,  in rockchip_soc_hlvl_pwr_dm_on_finish()  argument
94 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,  in rockchip_soc_hlvl_pwr_dm_resume()  argument
216 	uint32_t lvl;  in rockchip_pwr_domain_off()  local
229 	for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {  in rockchip_pwr_domain_off()
230 		lvl_state = target_state->pwr_domain_state[lvl];  in rockchip_pwr_domain_off()
231 		ret = rockchip_soc_hlvl_pwr_dm_off(lvl, lvl_state);  in rockchip_pwr_domain_off()
243 	uint32_t lvl;  in rockchip_pwr_domain_suspend()  local
265 	for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {  in rockchip_pwr_domain_suspend()
266 		lvl_state = target_state->pwr_domain_state[lvl];  in rockchip_pwr_domain_suspend()
267 		ret = rockchip_soc_hlvl_pwr_dm_suspend(lvl, lvl_state);  in rockchip_pwr_domain_suspend()
280 	uint32_t lvl;  in rockchip_pwr_domain_on_finish()  local
286 	for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {  in rockchip_pwr_domain_on_finish()
287 		lvl_state = target_state->pwr_domain_state[lvl];  in rockchip_pwr_domain_on_finish()
288 		ret = rockchip_soc_hlvl_pwr_dm_on_finish(lvl, lvl_state);  in rockchip_pwr_domain_on_finish()
317 	uint32_t lvl;  in rockchip_pwr_domain_suspend_finish()  local
330 	for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {  in rockchip_pwr_domain_suspend_finish()
331 		lvl_state = target_state->pwr_domain_state[lvl];  in rockchip_pwr_domain_suspend_finish()
332 		ret = rockchip_soc_hlvl_pwr_dm_resume(lvl, lvl_state);  in rockchip_pwr_domain_suspend_finish()