| /rk3399_ARM-atf/drivers/arm/gic/v2/ |
| H A D | gicv2_main.c | 40 assert(driver_data->gicc_base != 0U); in gicv2_cpuif_enable()
50 gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK); in gicv2_cpuif_enable()
51 gicc_write_ctlr(driver_data->gicc_base, val); in gicv2_cpuif_enable()
63 assert(driver_data->gicc_base != 0U); in gicv2_cpuif_disable()
66 val = gicc_read_ctlr(driver_data->gicc_base); in gicv2_cpuif_disable()
70 gicc_write_ctlr(driver_data->gicc_base, val); in gicv2_cpuif_disable()
134 assert(plat_driver_data->gicc_base != 0U); in gicv2_driver_init()
183 assert(driver_data->gicc_base != 0U); in gicv2_is_fiq_enabled()
185 gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base); in gicv2_is_fiq_enabled()
200 assert(driver_data->gicc_base != 0U); in gicv2_get_pending_interrupt_type()
[all …]
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| H A D | gicv2_base.c | 31 .gicc_base = PLAT_ARM_GICC_BASE,
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| /rk3399_ARM-atf/plat/nxp/soc-ls1043a/ |
| H A D | soc.c | 360 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base) in get_gic_offset() argument
372 *gicc_base = NXP_GICC_4K_ADDR; in get_gic_offset()
375 *gicc_base = NXP_GICC_64K_ADDR; in get_gic_offset()
379 *gicc_base = NXP_GICC_4K_ADDR; in get_gic_offset()
396 static uint32_t gicc_base, gicd_base; in soc_platform_setup() local
398 get_gic_offset(&gicc_base, &gicd_base); in soc_platform_setup()
399 plat_ls_gic_driver_init(gicd_base, gicc_base, in soc_platform_setup()
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| /rk3399_ARM-atf/plat/qemu/common/ |
| H A D | qemu_gicv2.c | 18 .gicc_base = GICC_BASE,
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| /rk3399_ARM-atf/plat/nuvoton/common/ |
| H A D | plat_nuvoton_gic.c | 21 .gicc_base = BASE_GICC_BASE,
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| /rk3399_ARM-atf/plat/rockchip/common/ |
| H A D | rockchip_gicv2.c | 38 .gicc_base = PLAT_RK_GICC_BASE,
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| /rk3399_ARM-atf/plat/hisilicon/poplar/ |
| H A D | poplar_gicv2.c | 25 .gicc_base = POPLAR_GICC_BASE,
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| /rk3399_ARM-atf/plat/nvidia/tegra/common/ |
| H A D | tegra_gicv2.c | 36 tegra_gic_data.gicc_base = TEGRA_GICC_BASE; in tegra_gic_setup()
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| /rk3399_ARM-atf/drivers/nxp/gic/ |
| H A D | ls_gicv2.c | 25 ls_gic_data.gicc_base = nxp_gicc_addr; in plat_ls_gic_driver_init()
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| /rk3399_ARM-atf/plat/common/ |
| H A D | plat_gicv2_base.c | 35 .gicc_base = PLAT_ARM_GICC_BASE,
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| /rk3399_ARM-atf/include/drivers/nxp/gic/gicv2/ |
| H A D | plat_gic.h | 69 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
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| /rk3399_ARM-atf/plat/qti/msm8916/ |
| H A D | msm8916_gicv2.c | 47 .gicc_base = APCS_QGIC2_GICC,
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| /rk3399_ARM-atf/plat/st/common/ |
| H A D | stm32mp_gic.c | 71 platform_gic_data.gicc_base = addr; in stm32mp_gic_init()
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| /rk3399_ARM-atf/plat/marvell/armada/common/ |
| H A D | marvell_gicv2.c | 59 .gicc_base = PLAT_MARVELL_GICC_BASE,
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| /rk3399_ARM-atf/plat/amlogic/gxbb/ |
| H A D | gxbb_bl31_setup.c | 129 .gicc_base = AML_GICC_BASE,
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| /rk3399_ARM-atf/plat/rpi/common/ |
| H A D | rpi4_bl31_setup.c | 35 .gicc_base = RPI4_GIC_GICC_BASE,
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| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hikey_bl31_setup.c | 50 .gicc_base = PLAT_ARM_GICC_BASE,
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| /rk3399_ARM-atf/plat/amlogic/g12a/ |
| H A D | g12a_bl31_setup.c | 129 .gicc_base = AML_GICC_BASE,
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| /rk3399_ARM-atf/plat/allwinner/common/ |
| H A D | sunxi_bl31_setup.c | 38 .gicc_base = SUNXI_GICC_BASE,
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| /rk3399_ARM-atf/plat/qemu/common/sp_min/ |
| H A D | sp_min_setup.c | 63 .gicc_base = GICC_BASE,
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| /rk3399_ARM-atf/plat/amlogic/gxl/ |
| H A D | gxl_bl31_setup.c | 165 .gicc_base = AML_GICC_BASE,
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| /rk3399_ARM-atf/plat/amlogic/axg/ |
| H A D | axg_bl31_setup.c | 155 .gicc_base = AML_GICC_BASE,
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| /rk3399_ARM-atf/include/drivers/arm/ |
| H A D | gicv2.h | 164 uintptr_t gicc_base; member
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| /rk3399_ARM-atf/plat/intel/soc/n5x/ |
| H A D | bl31_plat_setup.c | 95 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/ |
| H A D | bl31_plat_setup.c | 102 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
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