1*050a99a6SPankaj Gupta /* 2*050a99a6SPankaj Gupta * Copyright 2021 NXP 3*050a99a6SPankaj Gupta * 4*050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*050a99a6SPankaj Gupta * 6*050a99a6SPankaj Gupta */ 7*050a99a6SPankaj Gupta 8*050a99a6SPankaj Gupta #ifndef PLAT_GICV2_H 9*050a99a6SPankaj Gupta #define PLAT_GICV2_H 10*050a99a6SPankaj Gupta 11*050a99a6SPankaj Gupta #include <drivers/arm/gicv2.h> 12*050a99a6SPankaj Gupta 13*050a99a6SPankaj Gupta /* register offsets */ 14*050a99a6SPankaj Gupta #define GICD_CTLR_OFFSET 0x0 15*050a99a6SPankaj Gupta #define GICD_CPENDSGIR3_OFFSET 0xF1C 16*050a99a6SPankaj Gupta #define GICD_SPENDSGIR3_OFFSET 0xF2C 17*050a99a6SPankaj Gupta #define GICD_SGIR_OFFSET 0xF00 18*050a99a6SPankaj Gupta #define GICD_IGROUPR0_OFFSET 0x080 19*050a99a6SPankaj Gupta #define GICD_TYPER_OFFSET 0x0004 20*050a99a6SPankaj Gupta #define GICD_ISENABLER0_OFFSET 0x0100 21*050a99a6SPankaj Gupta #define GICD_ICENABLER0_OFFSET 0x0180 22*050a99a6SPankaj Gupta #define GICD_IPRIORITYR3_OFFSET 0x040C 23*050a99a6SPankaj Gupta #define GICD_ISENABLERn_OFFSET 0x0100 24*050a99a6SPankaj Gupta #define GICD_ISACTIVER0_OFFSET 0x300 25*050a99a6SPankaj Gupta 26*050a99a6SPankaj Gupta #define GICC_CTLR_OFFSET 0x0 27*050a99a6SPankaj Gupta #define GICC_PMR_OFFSET 0x0004 28*050a99a6SPankaj Gupta #define GICC_IAR_OFFSET 0x000C 29*050a99a6SPankaj Gupta #define GICC_DIR_OFFSET 0x1000 30*050a99a6SPankaj Gupta #define GICC_EOIR_OFFSET 0x0010 31*050a99a6SPankaj Gupta 32*050a99a6SPankaj Gupta /* bitfield masks */ 33*050a99a6SPankaj Gupta #define GICC_CTLR_EN_GRP0 0x1 34*050a99a6SPankaj Gupta #define GICC_CTLR_EN_GRP1 0x2 35*050a99a6SPankaj Gupta #define GICC_CTLR_EOImodeS_MASK 0x200 36*050a99a6SPankaj Gupta #define GICC_CTLR_DIS_BYPASS 0x60 37*050a99a6SPankaj Gupta #define GICC_CTLR_CBPR_MASK 0x10 38*050a99a6SPankaj Gupta #define GICC_CTLR_FIQ_EN_MASK 0x8 39*050a99a6SPankaj Gupta #define GICC_CTLR_ACKCTL_MASK 0x4 40*050a99a6SPankaj Gupta #define GICC_PMR_FILTER 0xFF 41*050a99a6SPankaj Gupta 42*050a99a6SPankaj Gupta #define GICD_CTLR_EN_GRP0 0x1 43*050a99a6SPankaj Gupta #define GICD_CTLR_EN_GRP1 0x2 44*050a99a6SPankaj Gupta #define GICD_IGROUP0_SGI15 0x8000 45*050a99a6SPankaj Gupta #define GICD_ISENABLE0_SGI15 0x8000 46*050a99a6SPankaj Gupta #define GICD_ICENABLE0_SGI15 0x8000 47*050a99a6SPankaj Gupta #define GICD_ISACTIVER0_SGI15 0x8000 48*050a99a6SPankaj Gupta #define GICD_CPENDSGIR_CLR_MASK 0xFF000000 49*050a99a6SPankaj Gupta #define GICD_IPRIORITY_SGI15_MASK 0xFF000000 50*050a99a6SPankaj Gupta #define GICD_SPENDSGIR3_SGI15_MASK 0xFF000000 51*050a99a6SPankaj Gupta #define GICD_SPENDSGIR3_SGI15_OFFSET 0x18 52*050a99a6SPankaj Gupta 53*050a99a6SPankaj Gupta #ifndef __ASSEMBLER__ 54*050a99a6SPankaj Gupta 55*050a99a6SPankaj Gupta /* GIC common API's */ 56*050a99a6SPankaj Gupta void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr, 57*050a99a6SPankaj Gupta const uintptr_t nxp_gicc_addr, 58*050a99a6SPankaj Gupta uint8_t plat_core_count, 59*050a99a6SPankaj Gupta interrupt_prop_t *ls_interrupt_props, 60*050a99a6SPankaj Gupta uint8_t ls_interrupt_prop_count, 61*050a99a6SPankaj Gupta uint32_t *target_mask_array); 62*050a99a6SPankaj Gupta void plat_ls_gic_init(void); 63*050a99a6SPankaj Gupta void plat_ls_gic_cpuif_enable(void); 64*050a99a6SPankaj Gupta void plat_ls_gic_cpuif_disable(void); 65*050a99a6SPankaj Gupta void plat_ls_gic_redistif_on(void); 66*050a99a6SPankaj Gupta void plat_ls_gic_redistif_off(void); 67*050a99a6SPankaj Gupta void plat_gic_pcpu_init(void); 68*050a99a6SPankaj Gupta /* GIC utility functions */ 69*050a99a6SPankaj Gupta void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base); 70*050a99a6SPankaj Gupta #endif 71*050a99a6SPankaj Gupta 72*050a99a6SPankaj Gupta #endif /* PLAT_GICV2_H */ 73