1 /*
2 * Copyright (c) 2018-2025, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #include <assert.h>
7 #include <common/bl_common.h>
8 #ifdef AML_STDPARAMS
9 #include <common/desc_image_load.h>
10 #endif
11 #include <common/interrupt_props.h>
12 #include <drivers/arm/gicv2.h>
13 #include <lib/mmio.h>
14 #include <lib/xlat_tables/xlat_mmu_helpers.h>
15 #include <plat/common/platform.h>
16 #include <platform_def.h>
17
18 #include "aml_private.h"
19
20 /*
21 * Placeholder variables for copying the arguments that have been passed to
22 * BL31 from BL2.
23 */
24 static entry_point_info_t bl33_image_ep_info;
25 static image_info_t bl30_image_info;
26 static image_info_t bl301_image_info;
27
28 /*******************************************************************************
29 * Return a pointer to the 'entry_point_info' structure of the next image for
30 * the security state specified. BL33 corresponds to the non-secure image type
31 * while BL32 corresponds to the secure image type. A NULL pointer is returned
32 * if the image does not exist.
33 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)34 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
35 {
36 entry_point_info_t *next_image_info;
37
38 assert(type == NON_SECURE);
39
40 next_image_info = &bl33_image_ep_info;
41
42 /* None of the images can have 0x0 as the entrypoint. */
43 if (next_image_info->pc != 0U) {
44 return next_image_info;
45 } else {
46 return NULL;
47 }
48 }
49
50 /*******************************************************************************
51 * Perform any BL31 early platform setup. Here is an opportunity to copy
52 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before
53 * they are lost (potentially). This needs to be done before the MMU is
54 * initialized so that the memory layout can be used while creating page
55 * tables. BL2 has flushed this information to memory, so we are guaranteed
56 * to pick up good data.
57 ******************************************************************************/
58 struct gxl_bl31_param {
59 param_header_t h;
60 image_info_t *bl31_image_info;
61 entry_point_info_t *bl32_ep_info;
62 image_info_t *bl32_image_info;
63 entry_point_info_t *bl33_ep_info;
64 image_info_t *bl33_image_info;
65 #ifndef AML_STDPARAMS
66 image_info_t *scp_image_info[];
67 #endif
68 };
69
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)70 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
71 u_register_t arg2, u_register_t arg3)
72 {
73 #ifndef AML_STDPARAMS
74 struct gxl_bl31_param *from_bl2;
75 #endif
76
77 /* Initialize the console to provide early debug support */
78 aml_console_init();
79
80 #ifdef AML_STDPARAMS
81 /* Parse arguments passed to BL31 from U-Boot SPL */
82 bl31_params_parse_helper(arg0, &bl33_image_ep_info,
83 &bl33_image_ep_info);
84 #else
85 /* Check that params passed from BL2 are not NULL. */
86 from_bl2 = (struct gxl_bl31_param *) arg0;
87
88 /* Check params passed from BL2 are not NULL. */
89 assert(from_bl2 != NULL);
90 assert(from_bl2->h.type == PARAM_BL31);
91 assert(from_bl2->h.version >= VERSION_1);
92
93 /*
94 * Copy BL33 entry point information. It is stored in Secure RAM, in
95 * BL2's address space.
96 */
97 bl33_image_ep_info = *from_bl2->bl33_ep_info;
98 #endif
99
100 if (bl33_image_ep_info.pc == 0U) {
101 ERROR("BL31: BL33 entrypoint not obtained from BL2\n");
102 panic();
103 }
104
105 #ifdef AML_STDPARAMS
106 /* Hardcode SCP_BL2 image info */
107 bl30_image_info.image_base = 0x13c0000;
108 bl30_image_info.image_size = 0xa000;
109 bl301_image_info.image_base = 0x13ca000;
110 bl301_image_info.image_size = 0x3400;
111 #else
112 bl30_image_info = *from_bl2->scp_image_info[0];
113 bl301_image_info = *from_bl2->scp_image_info[1];
114 #endif
115 }
116
bl31_plat_arch_setup(void)117 void bl31_plat_arch_setup(void)
118 {
119 aml_setup_page_tables();
120
121 enable_mmu_el3(0);
122 }
123
gxl_scp_ready(void)124 static inline bool gxl_scp_ready(void)
125 {
126 return AML_AO_RTI_SCP_IS_READY(mmio_read_32(AML_AO_RTI_SCP_STAT));
127 }
128
gxl_scp_boot(void)129 static inline void gxl_scp_boot(void)
130 {
131 aml_scpi_upload_scp_fw(bl30_image_info.image_base,
132 bl30_image_info.image_size, 0);
133 aml_scpi_upload_scp_fw(bl301_image_info.image_base,
134 bl301_image_info.image_size, 1);
135 while (!gxl_scp_ready())
136 ;
137 }
138
139 /*******************************************************************************
140 * GICv2 driver setup information
141 ******************************************************************************/
142 static const interrupt_prop_t gxl_interrupt_props[] = {
143 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
144 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
145 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
146 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
147 INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
148 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
149 INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
150 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
151 INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
152 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
153 INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
154 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
155 INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
156 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
157 INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
158 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
159 INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
160 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
161 };
162
163 static const gicv2_driver_data_t gxl_gic_data = {
164 .gicd_base = AML_GICD_BASE,
165 .gicc_base = AML_GICC_BASE,
166 .interrupt_props = gxl_interrupt_props,
167 .interrupt_props_num = ARRAY_SIZE(gxl_interrupt_props),
168 };
169
bl31_platform_setup(void)170 void bl31_platform_setup(void)
171 {
172 aml_mhu_secure_init();
173
174 gicv2_driver_init(&gxl_gic_data);
175 gicv2_distif_init();
176 gicv2_pcpu_distif_init();
177 gicv2_cpuif_enable();
178
179 gxl_scp_boot();
180
181 aml_thermal_unknown();
182 }
183