1 /*
2 * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <libfdt.h>
10
11 #include <platform_def.h>
12
13 #include <arch.h>
14 #include <arch_helpers.h>
15 #include <common/debug.h>
16 #include <common/fdt_fixup.h>
17 #include <drivers/arm/gicv2.h>
18 #include <drivers/console.h>
19 #include <drivers/generic_delay_timer.h>
20 #include <drivers/ti/uart/uart_16550.h>
21 #include <lib/mmio.h>
22 #include <plat/common/platform.h>
23
24 #include <sunxi_def.h>
25 #include <sunxi_mmap.h>
26 #include <sunxi_private.h>
27
28
29 static entry_point_info_t bl32_image_ep_info;
30 static entry_point_info_t bl33_image_ep_info;
31
32 static console_t console;
33
34 static void *fdt;
35
36 static const gicv2_driver_data_t sunxi_gic_data = {
37 .gicd_base = SUNXI_GICD_BASE,
38 .gicc_base = SUNXI_GICC_BASE,
39 };
40
41 /*
42 * Try to find a DTB loaded in memory by previous stages.
43 *
44 * At the moment we implement a heuristic to find the DTB attached to U-Boot:
45 * U-Boot appends its DTB to the end of the image. Assuming that BL33 is
46 * U-Boot, try to find the size of the U-Boot image to learn the DTB address.
47 * The generic ARMv8 U-Boot image contains the load address and its size
48 * as u64 variables at the beginning of the image. There might be padding
49 * or other headers before that data, so scan the first 2KB after the BL33
50 * entry point to find the load address, which should be followed by the
51 * size. Adding those together gives us the address of the DTB.
52 */
sunxi_find_dtb(void)53 static void sunxi_find_dtb(void)
54 {
55 uint64_t *u_boot_base;
56 int i;
57
58 u_boot_base = (void *)SUNXI_BL33_VIRT_BASE;
59
60 for (i = 0; i < 2048 / sizeof(uint64_t); i++) {
61 void *dtb_base;
62
63 if (u_boot_base[i] != PRELOADED_BL33_BASE)
64 continue;
65
66 /* Does the suspected U-Boot size look anyhow reasonable? */
67 if (u_boot_base[i + 1] >= 256 * 1024 * 1024)
68 continue;
69
70 /* end of the image: base address + size */
71 dtb_base = (char *)u_boot_base + u_boot_base[i + 1];
72
73 if (fdt_check_header(dtb_base) == 0) {
74 fdt = dtb_base;
75 return;
76 }
77 }
78 }
79
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)80 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
81 u_register_t arg2, u_register_t arg3)
82 {
83 /* Initialize the debug console as soon as possible */
84 console_16550_register(SUNXI_UART0_BASE, SUNXI_UART0_CLK_IN_HZ,
85 SUNXI_UART0_BAUDRATE, &console);
86
87 #ifdef BL32_BASE
88 /* Populate entry point information for BL32 */
89 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
90 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
91 bl32_image_ep_info.pc = BL32_BASE;
92 #endif
93
94 /* Populate entry point information for BL33 */
95 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
96 /*
97 * Tell BL31 where the non-trusted software image
98 * is located and the entry state information
99 */
100 bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
101 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
102 DISABLE_ALL_EXCEPTIONS);
103 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
104 }
105
bl31_plat_arch_setup(void)106 void bl31_plat_arch_setup(void)
107 {
108 sunxi_configure_mmu_el3(0);
109 }
110
bl31_platform_setup(void)111 void bl31_platform_setup(void)
112 {
113 const char *soc_name;
114 uint16_t soc_id = sunxi_read_soc_id();
115
116 switch (soc_id) {
117 case SUNXI_SOC_A64:
118 soc_name = "A64/H64/R18";
119 break;
120 case SUNXI_SOC_H5:
121 soc_name = "H5";
122 break;
123 case SUNXI_SOC_H6:
124 soc_name = "H6";
125 break;
126 case SUNXI_SOC_H616:
127 soc_name = "H616";
128 break;
129 case SUNXI_SOC_R329:
130 soc_name = "R329";
131 break;
132 default:
133 soc_name = "unknown";
134 break;
135 }
136 NOTICE("BL31: Detected Allwinner %s SoC (%04x)\n", soc_name, soc_id);
137
138 generic_delay_timer_init();
139
140 sunxi_find_dtb();
141 if (fdt) {
142 const char *model;
143 int length;
144
145 model = fdt_getprop(fdt, 0, "model", &length);
146 NOTICE("BL31: Found U-Boot DTB at %p, model: %s\n", fdt,
147 model ?: "unknown");
148 } else {
149 NOTICE("BL31: No DTB found.\n");
150 }
151
152 /* Configure the interrupt controller */
153 gicv2_driver_init(&sunxi_gic_data);
154 gicv2_distif_init();
155 gicv2_pcpu_distif_init();
156 gicv2_cpuif_enable();
157
158 sunxi_security_setup();
159
160 /*
161 * On the A64 U-Boot's SPL sets the bus clocks to some conservative
162 * values, to work around FEL mode instabilities with SRAM C accesses.
163 * FEL mode is gone when we reach ATF, so bring the AHB1 bus
164 * (the "main" bus) clock frequency back to the recommended 200MHz,
165 * for improved performance.
166 */
167 if (soc_id == SUNXI_SOC_A64)
168 mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x00003180);
169
170 /*
171 * U-Boot or the kernel don't setup AHB2, which leaves it at the
172 * AHB1 frequency (200 MHz, see above). However Allwinner recommends
173 * 300 MHz, for improved Ethernet and USB performance. Switch the
174 * clock to use "PLL_PERIPH0 / 2".
175 */
176 if (soc_id == SUNXI_SOC_A64 || soc_id == SUNXI_SOC_H5)
177 mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0x1);
178
179 sunxi_pmic_setup(soc_id, fdt);
180
181 INFO("BL31: Platform setup done\n");
182 }
183
bl31_plat_runtime_setup(void)184 void bl31_plat_runtime_setup(void)
185 {
186 /* Change the DTB if the configuration requires so. */
187 sunxi_prepare_dtb(fdt);
188 }
189
bl31_plat_get_next_image_ep_info(uint32_t type)190 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
191 {
192 assert(sec_state_is_valid(type) != 0);
193
194 if (type == NON_SECURE)
195 return &bl33_image_ep_info;
196
197 if ((type == SECURE) && bl32_image_ep_info.pc)
198 return &bl32_image_ep_info;
199
200 return NULL;
201 }
202