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Searched refs:io_read32 (Results 1 – 25 of 150) sorted by relevance

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/optee_os/core/drivers/
H A Dls_sec_mon.c124 data->hplr = io_read32((vaddr_t)&sec_mon_regs->hplr); in ls_sec_mon_read()
125 data->hpcomr = io_read32((vaddr_t)&sec_mon_regs->hpcomr); in ls_sec_mon_read()
126 data->hpsicr = io_read32((vaddr_t)&sec_mon_regs->hpsicr); in ls_sec_mon_read()
127 data->hpsvcr = io_read32((vaddr_t)&sec_mon_regs->hpsvcr); in ls_sec_mon_read()
128 data->hpsr = io_read32((vaddr_t)&sec_mon_regs->hpsr); in ls_sec_mon_read()
129 data->hpsvsr = io_read32((vaddr_t)&sec_mon_regs->hpsvsr); in ls_sec_mon_read()
130 data->hphacivr = io_read32((vaddr_t)&sec_mon_regs->hphacivr); in ls_sec_mon_read()
131 data->hphacr = io_read32((vaddr_t)&sec_mon_regs->hphacr); in ls_sec_mon_read()
132 data->lplr = io_read32((vaddr_t)&sec_mon_regs->lplr); in ls_sec_mon_read()
133 data->lpcr = io_read32((vaddr_t)&sec_mon_regs->lpcr); in ls_sec_mon_read()
[all …]
H A Dls_sfp.c179 while (io_read32(sfp_ingr_va) & SFP_INGR_PROGFB_CMD) { in ls_sfp_program_fuses()
197 if (io_read32(sfp_ingr_va) & SFP_INGR_ERROR_MASK) { in ls_sfp_program_fuses()
217 data->ingr = io_read32((vaddr_t)&sfp_regs->ingr); in ls_sfp_read()
218 data->svhesr = io_read32((vaddr_t)&sfp_regs->svhesr); in ls_sfp_read()
219 data->sfpcr = io_read32((vaddr_t)&sfp_regs->sfpcr); in ls_sfp_read()
220 data->version = io_read32((vaddr_t)&sfp_regs->version); in ls_sfp_read()
221 data->ospr0 = io_read32((vaddr_t)&sfp_regs->ospr0); in ls_sfp_read()
222 data->ospr1 = io_read32((vaddr_t)&sfp_regs->ospr1); in ls_sfp_read()
223 data->dcvr0 = io_read32((vaddr_t)&sfp_regs->dcvr0); in ls_sfp_read()
224 data->dcvr1 = io_read32((vaddr_t)&sfp_regs->dcvr1); in ls_sfp_read()
[all …]
H A Dtzc380.c57 return io_read32(base + BUILD_CONFIG_OFF); in tzc_read_build_config()
67 return io_read32(base + ACTION_OFF); in tzc_read_action()
84 return io_read32(base + REGION_ATTRIBUTES_OFF(region)); in tzc_read_region_attributes()
146 io_read32(base + FAIL_ADDRESS_LOW_OFF)); in tzc_fail_dump()
148 io_read32(base + FAIL_ADDRESS_HIGH_OFF)); in tzc_fail_dump()
149 EMSG("Fail Control 0x%" PRIx32, io_read32(base + FAIL_CONTROL_OFF)); in tzc_fail_dump()
150 EMSG("Fail Id 0x%" PRIx32, io_read32(base + FAIL_ID)); in tzc_fail_dump()
305 check = io_read32(tzc.base + LOCKDOWN_RANGE_OFF); in tzc_regions_lockdown()
311 check = io_read32(tzc.base + LOCKDOWN_SELECT_OFF); in tzc_regions_lockdown()
322 return io_read32(base + REGION_SETUP_LOW_OFF(region)); in tzc_read_region_base_low()
[all …]
H A Dstm32_rng.c133 uint32_t sr = io_read32(rng_base + RNG_SR); in conceal_seed_error_cond_reset()
153 if (io_read32(rng_base + RNG_CR) & RNG_CR_CONDRST) { in conceal_seed_error_cond_reset()
162 if (io_read32(rng_base + RNG_SR) & RNG_SR_SEIS) in conceal_seed_error_cond_reset()
166 if (io_read32(rng_base + RNG_SR) & RNG_SR_SECS) { in conceal_seed_error_cond_reset()
201 (void)io_read32(rng_base + RNG_DR); in conceal_seed_error_sw_reset()
203 if (io_read32(rng_base + RNG_SR) & RNG_SR_SEIS) in conceal_seed_error_sw_reset()
222 if (dev->error_conceal || io_read32(rng_base + RNG_SR) & RNG_SR_SEIS) in read_available()
225 if (!(io_read32(rng_base + RNG_SR) & RNG_SR_DRDY)) { in read_available()
230 if (io_read32(rng_base + RNG_SR) & RNG_SR_SEIS) { in read_available()
244 if (!(io_read32(rng_base + RNG_SR) & RNG_SR_DRDY)) in read_available()
[all …]
H A Dimx_snvs.c72 hp_mks = io_read32(base + SNVS_HPCOMR); in is_otpmk_selected()
79 uint32_t lp_mks = io_read32(base + SNVS_LPMKCR); in is_otpmk_selected()
95 return io_read32(base + SNVS_HPLR) & SNVS_HPLR_MKS_SL || in is_mks_locked()
96 io_read32(base + SNVS_LPLR) & SNVS_LPLR_MKS_HL; in is_mks_locked()
116 uint32_t status = io_read32(base + SNVS_HPSR); in is_otpmk_valid()
127 val = (io_read32(base + SNVS_HPSR) & SNVS_HPSR_SYS_SECURITY_CFG) >> in snvs_get_security_cfg()
154 val = io_read32(snvs + SNVS_HPSR); in snvs_get_ssm_mode()
H A Ddra7_rng.c79 while (!(io_read32(rng + RNG_STATUS) & RNG_READY)) { in dra7_rng_read64()
81 if (io_read32(rng + RNG_STATUS) & SHUTDOWN_OFLO) { in dra7_rng_read64()
82 uint32_t alarm = io_read32(rng + RNG_ALARMSTOP); in dra7_rng_read64()
83 uint32_t tune = io_read32(rng + RNG_FRODETUNE); in dra7_rng_read64()
99 *low_word = io_read32(rng + RNG_OUTPUT_L); in dra7_rng_read64()
100 *high_word = io_read32(rng + RNG_OUTPUT_H); in dra7_rng_read64()
143 while (io_read32(rng + RNG_SOFT_RESET_REG) & RNG_SOFT_RESET) in dra7_rng_init()
H A Dlpc_uart.c33 status = io_read32(LPC_IRQ_ST_REG_OFFSET + addr); in lpc_byte_read()
38 status = io_read32(LPC_IRQ_ST_REG_OFFSET + addr); in lpc_byte_read()
43 if (io_read32(LPC_OP_STATUS_REG_OFFSET + addr) & LPC_IRQ_ST_ON) in lpc_byte_read()
44 *data = io_read32(LPC_RDATA_REG_OFFSET + addr); in lpc_byte_read()
59 status = io_read32(LPC_IRQ_ST_REG_OFFSET + addr); in lpc_byte_write()
64 status = io_read32(LPC_IRQ_ST_REG_OFFSET + addr); in lpc_byte_write()
H A Dtzc400.c84 return io_read32(base + BUILD_CONFIG_OFF); in tzc_read_build_config()
89 return io_read32(base + GATE_KEEPER_OFF); in tzc_read_gate_keeper()
104 return io_read32(base + REGION_BASE_LOW_OFF + REGION_NUM_OFF(region)); in tzc_read_region_base_low()
115 return io_read32(base + REGION_BASE_HIGH_OFF + REGION_NUM_OFF(region)); in tzc_read_region_base_high()
126 return io_read32(base + REGION_TOP_LOW_OFF + REGION_NUM_OFF(region)); in tzc_read_region_top_low()
137 return io_read32(base + REGION_TOP_HIGH_OFF + REGION_NUM_OFF(region)); in tzc_read_region_top_high()
148 return io_read32(base + REGION_ATTRIBUTES_OFF + REGION_NUM_OFF(region)); in tzc_read_region_attributes()
159 return io_read32(base + REGION_ID_ACCESS_OFF + REGION_NUM_OFF(region)); in tzc_read_region_id_access()
387 return io_read32(tzc.base + FAIL_CONTROL(filter)) & in write_not_read()
393 return io_read32(tzc.base + FAIL_CONTROL(filter)) & in nonsecure_not_secure()
[all …]
H A Datmel_uart.c65 while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXEMPTY)) in atmel_uart_flush()
73 while (io_read32(base + ATMEL_UART_SR) & ATMEL_SR_RXRDY) in atmel_uart_getchar()
76 return io_read32(base + ATMEL_UART_RHR); in atmel_uart_getchar()
83 while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXRDY)) in atmel_uart_putc()
H A Damlogic_uart.c37 while (!(io_read32(base + AML_UART_STATUS) & AML_UART_TX_EMPTY)) in amlogic_uart_flush()
45 if (io_read32(base + AML_UART_STATUS) & AML_UART_RX_EMPTY) in amlogic_uart_getchar()
48 return io_read32(base + AML_UART_RFIFO) & 0xff; in amlogic_uart_getchar()
55 while (io_read32(base + AML_UART_STATUS) & AML_UART_TX_FULL) in amlogic_uart_putc()
H A Dimx_uart.c100 while (!(io_read32(base + UTS) & UTS_TXEMPTY)) in imx_uart_flush()
101 if (!(io_read32(base + UCR1) & UCR1_UARTEN)) in imx_uart_flush()
109 while (io_read32(base + UTS) & UTS_RXEMPTY) in imx_uart_getchar()
112 return (io_read32(base + URXD) & URXD_RX_DATA); in imx_uart_getchar()
120 while (io_read32(base + UTS) & UTS_TXFULL) in imx_uart_putc()
121 if (!(io_read32(base + UCR1) & UCR1_UARTEN)) in imx_uart_putc()
H A Dxiphera_trng.c44 status = io_read32(xiphera_trng_base + STATUS_REG); in xiphera_trng_random_available()
53 value = io_read32(xiphera_trng_base + RAND_REG); in xiphera_trng_read32()
127 status = io_read32(xiphera_trng_base + STATUS_REG); in xiphera_trng_probe()
135 status = io_read32(xiphera_trng_base + STATUS_REG); in xiphera_trng_probe()
155 status = io_read32(xiphera_trng_base + STATUS_REG); in xiphera_trng_probe()
H A Dstm32_fmc.c96 return io_read32(fmc_d->base + _FMC_SECCFGR) & BIT(controller); in fmc_controller_is_secure()
109 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); in handle_available_semaphores()
114 if (!(io_read32(fmc_d->base + _FMC_SECCFGR) & BIT(i))) { in handle_available_semaphores()
200 if ((io_read32(fmc_d->base + _FMC_PRIVCFGR) & in apply_rif_config()
207 if ((io_read32(fmc_d->base + _FMC_SECCFGR) & in apply_rif_config()
324 uint32_t cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); in check_fmc_rif_conf()
325 uint32_t semcr = io_read32(fmc_d->base + _FMC_SEMCR(i)); in check_fmc_rif_conf()
357 semcr = io_read32(fmc_d->base + _FMC_SEMCR(0)); in configure_fmc()
358 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(0)); in configure_fmc()
434 io_read32(fmc_d->base + _FMC_CIDCFGR(i)) & in fmc_suspend()
[all …]
H A Dcdns_uart.c71 while (!(io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_flush()
80 return !(io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_have_rx_data()
90 return io_read32(base + CDNS_UART_FIFO) & 0xff; in cdns_uart_getchar()
98 while (io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_putc()
H A Dmvebu_uart.c76 while (!(io_read32(base + UART_STATUS_REG) & UARTLSR_TXFIFOEMPTY)) in mvebu_uart_flush()
84 return (io_read32(base + UART_STATUS_REG) & UART_RX_READY); in mvebu_uart_have_rx_data()
93 return io_read32(base + UART_RX_REG) & 0xff; in mvebu_uart_getchar()
103 tmp = io_read32(base + UART_STATUS_REG); in mvebu_uart_putc()
/optee_os/core/arch/arm/plat-k3/drivers/
H A Deip76d_trng.c69 return io_read32(rng + RNG_CONTROL) & ENABLE_TRNG; in eip76d_rng_is_enabled()
97 while (!(io_read32(rng + RNG_STATUS) & RNG_READY)) { in eip76d_rng_read128()
99 if (io_read32(rng + RNG_STATUS) & SHUTDOWN_OFLO) { in eip76d_rng_read128()
100 uint32_t alarm = io_read32(rng + RNG_ALARMSTOP); in eip76d_rng_read128()
101 uint32_t tune = io_read32(rng + RNG_FRODETUNE); in eip76d_rng_read128()
117 *word0 = io_read32(rng + RNG_OUTPUT_0); in eip76d_rng_read128()
118 *word1 = io_read32(rng + RNG_OUTPUT_1); in eip76d_rng_read128()
119 *word2 = io_read32(rng + RNG_OUTPUT_2); in eip76d_rng_read128()
120 *word3 = io_read32(rng + RNG_OUTPUT_3); in eip76d_rng_read128()
/optee_os/core/arch/arm/plat-telechips/drivers/
H A Dtcc_otp.c64 while (!(io_read32(reg + GENERAL_STATUS) & STATUS_READY)) in wait_for_ready()
70 while (!(io_read32(reg + OTP_CONTROL) & CTRL_DONE)) in wait_for_done()
91 admin_info0 = io_read32(reg + READ_ADMIN_INFO0); in tcc_otp_read_128()
93 if (!admin_info0 && !io_read32(reg + READ_STATUS)) in tcc_otp_read_128()
98 status = io_read32(reg + READ_STATUS); in tcc_otp_read_128()
104 buf[0] = io_read32(reg + READ_DATA_PAYLOAD0); in tcc_otp_read_128()
105 buf[1] = io_read32(reg + READ_DATA_PAYLOAD1); in tcc_otp_read_128()
106 buf[2] = io_read32(reg + READ_DATA_PAYLOAD2); in tcc_otp_read_128()
107 buf[3] = io_read32(reg + READ_DATA_PAYLOAD3); in tcc_otp_read_128()
123 if (io_read32(ctrl) & EXT_WP) { in tcc_otp_write_128()
/optee_os/core/drivers/clk/sam/
H A Dat91_pmc.c195 pmc_cache.scsr = io_read32(pmc_base + AT91_PMC_SCSR); in pmc_suspend()
196 pmc_cache.pcsr0 = io_read32(pmc_base + AT91_PMC_PCSR); in pmc_suspend()
197 pmc_cache.uckr = io_read32(pmc_base + AT91_CKGR_UCKR); in pmc_suspend()
198 pmc_cache.mor = io_read32(pmc_base + AT91_CKGR_MOR); in pmc_suspend()
199 pmc_cache.mcfr = io_read32(pmc_base + AT91_CKGR_MCFR); in pmc_suspend()
200 pmc_cache.pllar = io_read32(pmc_base + AT91_CKGR_PLLAR); in pmc_suspend()
201 pmc_cache.mckr = io_read32(pmc_base + AT91_PMC_MCKR); in pmc_suspend()
202 pmc_cache.usb = io_read32(pmc_base + AT91_PMC_USB); in pmc_suspend()
203 pmc_cache.imr = io_read32(pmc_base + AT91_PMC_IMR); in pmc_suspend()
204 pmc_cache.pcsr1 = io_read32(pmc_base + AT91_PMC_PCSR1); in pmc_suspend()
[all …]
H A Dat91_main.c39 uint32_t status = io_read32(osc->base + AT91_PMC_SR); in pmc_main_rc_osc_ready()
47 uint32_t mor = io_read32(osc->base + AT91_CKGR_MOR); in pmc_main_rc_osc_enable()
65 uint32_t mor = io_read32(osc->base + AT91_CKGR_MOR); in pmc_main_rc_osc_disable()
123 uint32_t status = io_read32(pmc->base + AT91_PMC_SR); in pmc_main_osc_ready()
131 uint32_t mor = io_read32(pmc->base + AT91_CKGR_MOR); in pmc_main_osc_enable()
152 uint32_t mor = io_read32(pmc->base + AT91_CKGR_MOR); in pmc_main_osc_disable()
198 while (!(io_read32(base + AT91_CKGR_MCFR) & AT91_PMC_MAINRDY)) in clk_main_probe_frequency()
213 mcfr = io_read32(base + AT91_CKGR_MCFR); in clk_main_get_rate()
222 uint32_t status = io_read32(base + AT91_PMC_SR); in clk_sam9x5_main_ready()
253 tmp = io_read32(pmc->base + AT91_CKGR_MOR); in clk_sam9x5_main_set_parent()
[all …]
/optee_os/core/arch/arm/plat-sunxi/
H A Dmain.c106 DMSG("SMTA_DECPORT0=%x", io_read32(v + REG_TZPC_SMTA_DECPORT0_STA_REG)); in tzpc_init()
107 DMSG("SMTA_DECPORT1=%x", io_read32(v + REG_TZPC_SMTA_DECPORT1_STA_REG)); in tzpc_init()
108 DMSG("SMTA_DECPORT2=%x", io_read32(v + REG_TZPC_SMTA_DECPORT2_STA_REG)); in tzpc_init()
115 DMSG("SMTA_DECPORT0=%x", io_read32(v + REG_TZPC_SMTA_DECPORT0_STA_REG)); in tzpc_init()
116 DMSG("SMTA_DECPORT1=%x", io_read32(v + REG_TZPC_SMTA_DECPORT1_STA_REG)); in tzpc_init()
117 DMSG("SMTA_DECPORT2=%x", io_read32(v + REG_TZPC_SMTA_DECPORT2_STA_REG)); in tzpc_init()
/optee_os/core/drivers/imx/mu/
H A Dimx_mu_8ulp_9x.c31 while (!(io_read32(addr) & mask)) in mu_wait_for()
35 if (io_read32(addr) & mask) in mu_wait_for()
45 return (io_read32(base + MU_PAR) & RR_NUM_MASK) >> RR_NUM_SHIFT; in imx_mu_plat_get_rx_channel()
50 return io_read32(base + MU_PAR) & TR_NUM_MASK; in imx_mu_plat_get_tx_channel()
74 *msg = io_read32(base + MU_RR(index)); in imx_mu_plat_receive()
/optee_os/core/arch/arm/plat-rockchip/
H A Dpsci_rk322x.c69 dram_d.cru_clkgate[i] = io_read32(va_base + CRU_CLKGATE_CON(i)); in clks_disable()
105 while (!(io_read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK) && in pll_wait_lock()
111 if (!(io_read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK)) { in pll_wait_lock()
125 dram_d.cru_clksel0 = io_read32(va_base + CRU_CLKSEL_CON(0)); in plls_power_down()
126 dram_d.cru_clksel1 = io_read32(va_base + CRU_CLKSEL_CON(1)); in plls_power_down()
127 dram_d.cru_clksel10 = io_read32(va_base + CRU_CLKSEL_CON(10)); in plls_power_down()
128 dram_d.cru_clksel21 = io_read32(va_base + CRU_CLKSEL_CON(21)); in plls_power_down()
129 dram_d.cru_mode_con = io_read32(va_base + CRU_MODE_CON); in plls_power_down()
209 while (!(io_read32(va_base + GRF_CPU_STATUS1) & wfei_mask) && in wait_core_wfe_i()
215 return io_read32(va_base + GRF_CPU_STATUS1) & wfei_mask; in wait_core_wfe_i()
[all …]
/optee_os/core/drivers/firewall/
H A Dstm32_risaf.c236 if (!io_read32(base + _RISAF_IASR)) in stm32_risaf_clear_illegal_access_flags()
255 if (!io_read32(base + _RISAF_IASR)) in stm32_risaf_print_erroneous_data()
261 io_read32(base + _RISAF_IAESR0)); in stm32_risaf_print_erroneous_data()
264 if (io_read32(base + _RISAF_IAESR1)) in stm32_risaf_print_erroneous_data()
266 io_read32(base + _RISAF_IAESR1)); in stm32_risaf_print_erroneous_data()
272 io_read32(base + _RISAF_IADDR0)); in stm32_risaf_print_erroneous_data()
275 if (io_read32(base + _RISAF_IADDR1)) in stm32_risaf_print_erroneous_data()
278 io_read32(base + _RISAF_IADDR1)); in stm32_risaf_print_erroneous_data()
281 io_read32(base + _RISAF_IADDR0)); in stm32_risaf_print_erroneous_data()
284 if (io_read32(base + _RISAF_IADDR1)) in stm32_risaf_print_erroneous_data()
[all …]
/optee_os/core/arch/arm/plat-stm32mp1/drivers/
H A Dstm32mp1_syscfg.c95 return io_read32(get_syscfg_base() + SYSCFG_IDC) & in stm32mp_syscfg_get_chip_dev_id()
106 if (io_read32(cmpcr_va) & SYSCFG_CMPCR_READY) in enable_io_compensation()
119 DMSG("SYSCFG.cmpcr = %#"PRIx32, io_read32(cmpcr_va)); in enable_io_compensation()
129 value_cmpcr = io_read32(cmpcr_base); in disable_io_compensation()
130 value_cmpcr2 = io_read32(cmpcr_base + CMPENSETR_OFFSET); in disable_io_compensation()
144 DMSG("SYSCFG.cmpcr = %#"PRIx32, io_read32(cmpcr_base)); in disable_io_compensation()
210 hlvs_value = io_read32(get_syscfg_base() + hslvenxr_offset) & in stm32mp_set_hslv_state()
/optee_os/core/arch/arm/plat-versal/
H A Dmain.c78 if (io_read32(plm_rtca + VERSAL_AHWROT_REG) == VERSAL_AHWROT_SECURED) in platform_banner()
81 if (io_read32(plm_rtca + VERSAL_SHWROT_REG) == VERSAL_SHWROT_SECURED) in platform_banner()
98 if (io_read32(plm_rtca + VERSAL_AHWROT_REG) == VERSAL_AHWROT_SECURED) in plat_rpmb_key_is_ready()
101 if (io_read32(plm_rtca + VERSAL_SHWROT_REG) == VERSAL_SHWROT_SECURED) in plat_rpmb_key_is_ready()

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