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Searched refs:div (Results 1 – 24 of 24) sorted by relevance

/optee_os/core/drivers/clk/sam/
H A Dclk-sam9x60-pll.c56 uint8_t div; member
276 uint32_t div, in sam9x60_div_pll_set_div() argument
288 SHIFT_U32(div, core->layout->div_shift) | ena_val); in sam9x60_div_pll_set_div()
302 static TEE_Result sam9x60_div_pll_set(struct sam9x60_div *div) in sam9x60_div_pll_set() argument
304 struct sam9x60_pll_core *core = &div->core; in sam9x60_div_pll_set()
315 if ((val & core->layout->endiv_mask) && cdiv == div->div) in sam9x60_div_pll_set()
318 return sam9x60_div_pll_set_div(core, div->div, 1); in sam9x60_div_pll_set()
323 struct sam9x60_div *div = hw->priv; in sam9x60_div_pll_prepare() local
325 return sam9x60_div_pll_set(div); in sam9x60_div_pll_prepare()
330 struct sam9x60_div *div = hw->priv; in sam9x60_div_pll_unprepare() local
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H A Dat91_master.c27 uint8_t div; member
52 uint8_t div = 1; in clk_master_div_get_rate() local
63 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_get_rate()
65 rate /= charac->divisors[div]; in clk_master_div_get_rate()
215 unsigned long div = 0; in clk_sama7g5_master_set_rate() local
217 div = UDIV_ROUND_NEAREST(parent_rate, rate); in clk_sama7g5_master_set_rate()
218 if (div > (1 << (MASTER_PRES_MAX - 1)) || in clk_sama7g5_master_set_rate()
219 (!IS_POWER_OF_TWO(div) && div != 3)) in clk_sama7g5_master_set_rate()
235 if (div == 3) in clk_sama7g5_master_set_rate()
236 master->div = MASTER_PRES_MAX; in clk_sama7g5_master_set_rate()
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H A Dat91_pll.c40 uint8_t div; member
65 uint8_t div = 0; in clk_pll_enable() local
69 div = PLL_DIV(pllr); in clk_pll_enable()
74 (div == pll->div && mul == pll->mul)) in clk_pll_enable()
86 pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) | in clk_pll_enable()
109 if (!pll->div || !pll->mul) in clk_pll_get_rate()
112 return (parent_rate / pll->div) * (pll->mul + 1); in clk_pll_get_rate()
117 uint32_t *div, uint32_t *mul, in clk_pll_get_best_div_mul() argument
217 if (div) in clk_pll_get_best_div_mul()
218 *div = bestdiv; in clk_pll_get_best_div_mul()
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H A Dat91_peripheral.c25 uint32_t div; member
53 periph->div = shift; in clk_sam9x5_peripheral_autodiv()
68 field_prep(periph->layout->div_mask, periph->div) | in clk_sam9x5_peripheral_enable()
104 periph->div = field_get(periph->layout->div_mask, status); in clk_sam9x5_peripheral_get_rate()
110 return parent_rate >> periph->div; in clk_sam9x5_peripheral_get_rate()
133 periph->div = shift; in clk_sam9x5_peripheral_set_rate()
171 periph->div = 0; in at91_clk_register_sam9x5_periph()
H A Dat91_usb.c63 unsigned long div = 1; in at91sam9x5_clk_usb_set_rate() local
68 div = UDIV_ROUND_NEAREST(parent_rate, rate); in at91sam9x5_clk_usb_set_rate()
69 if (div > SAM9X5_USB_MAX_DIV + 1 || !div) in at91sam9x5_clk_usb_set_rate()
73 (div - 1) << SAM9X5_USB_DIV_SHIFT); in at91sam9x5_clk_usb_set_rate()
H A Dat91_audio_pll.c46 #define AUDIO_PLL_QDPAD(qd, div) \ argument
49 (AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \
67 uint8_t div; member
105 AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div)); in clk_audio_pll_pad_enable()
175 if (apad_ck->qdaudio && apad_ck->div) in clk_audio_pll_pad_get_rate()
176 apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div); in clk_audio_pll_pad_get_rate()
254 apad_ck->div = 3; in clk_audio_pll_pad_set_rate()
257 apad_ck->div = 2; in clk_audio_pll_pad_set_rate()
H A Dat91_programmable.c98 unsigned long div = parent_rate / rate; in clk_programmable_set_rate() local
101 if (!div) in clk_programmable_set_rate()
105 shift = div - 1; in clk_programmable_set_rate()
110 shift = flsi(div) - 1; in clk_programmable_set_rate()
112 if (div != (1ULL << shift)) in clk_programmable_set_rate()
H A Dat91_generated.c103 uint32_t div = 1; in clk_generated_set_rate() local
111 div = UDIV_ROUND_NEAREST(parent_rate, rate); in clk_generated_set_rate()
112 if (div > GENERATED_MAX_DIV + 1 || !div) in clk_generated_set_rate()
115 gck->gckdiv = div - 1; in clk_generated_set_rate()
/optee_os/core/drivers/clk/
H A Dclk-stm32-core.c189 for (clkt = table; clkt->div; clkt++) in _get_table_div()
191 return clkt->div; in _get_table_div()
197 unsigned int div) in _get_table_val() argument
201 for (clkt = table; clkt->div; clkt++) in _get_table_val()
202 if (clkt->div == div) in _get_table_val()
228 unsigned int div, unsigned long flags, in _get_val() argument
232 return div; in _get_val()
235 return __builtin_ffs(div) - 1; in _get_val()
238 return (div != 0U) ? div : BIT(width); in _get_val()
241 return _get_table_val(table, div); in _get_val()
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H A Dclk-stm32-core.h26 unsigned int div; member
47 const struct div_cfg *div; member
59 unsigned int div; member
186 .div = _div,\
H A Dclk-stm32mp21.c599 { .val = 0, .div = 1 },
600 { .val = 1, .div = 2 },
601 { .val = 2, .div = 4 },
602 { .val = 3, .div = 8 },
603 { .val = 4, .div = 16 },
604 { .val = 5, .div = 16 },
605 { .val = 6, .div = 16 },
606 { .val = 7, .div = 16 },
1846 uint32_t div = (data & OBS_DIV_MASK) >> OBS_DIV_SHIFT; in stm32_clk_configure_obs() local
1870 val |= SHIFT_U32(div, RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT); in stm32_clk_configure_obs()
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H A Dclk-stm32mp25.c639 { .val = 0, .div = 1 },
640 { .val = 1, .div = 2 },
641 { .val = 2, .div = 4 },
642 { .val = 3, .div = 8 },
643 { .val = 4, .div = 16 },
644 { .val = 5, .div = 16 },
645 { .val = 6, .div = 16 },
646 { .val = 7, .div = 16 },
1850 uint32_t div = (data & OBS_DIV_MASK) >> OBS_DIV_SHIFT; in stm32_clk_configure_obs() local
1874 val |= SHIFT_U32(div, RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT); in stm32_clk_configure_obs()
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H A Dclk-stm32mp13.c77 uint32_t div; member
1625 opp_cfg->div = fdt_read_uint32_default(fdt, subnode, in stm32_clk_parse_fdt_opp()
2707 .div = dividers_mp13,
/optee_os/core/include/dt-bindings/clock/
H A Dstm32mp25-clksrc.h48 #define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\ argument
51 ((div) << CLK_DIV_SHIFT) |\
70 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
72 (div)))
229 #define OBS_CFG(id, status, int_ext, div, inv, sel)\ argument
234 ((div) << OBS_DIV_SHIFT) |\
259 #define OBS_INT_CFG(id, status, div, inv, sel)\ argument
260 OBS_CFG(id, status, OBS_INT, div, inv, sel)
262 #define OBS_EXT_CFG(id, status, div, inv, sel)\ argument
263 OBS_CFG(id, status, OBS_EXT, div, inv, sel)
H A Dstm32mp21-clksrc.h43 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
45 (div)))
182 #define OBS_CFG(id, status, int_ext, div, inv, sel)\ argument
187 ((div) << OBS_DIV_SHIFT) |\
212 #define OBS_INT_CFG(id, status, div, inv, sel)\ argument
213 OBS_CFG((id), (status), OBS_INT, (div), (inv), (sel))
215 #define OBS_EXT_CFG(id, status, div, inv, sel)\ argument
216 OBS_CFG((id), (status), OBS_EXT, (div), (inv), (sel))
H A Dstm32mp13-clksrc.h67 #define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
69 (div))
/optee_os/core/drivers/i2c/
H A Datmel_i2c.c217 long div = 0; in atmel_i2c_init_clk() local
228 div = UDIV_ROUND_NEAREST(clk, 2 * I2C_BUS_FREQ) - 3; in atmel_i2c_init_clk()
229 if (div < 0) in atmel_i2c_init_clk()
230 div = 0; in atmel_i2c_init_clk()
233 ckdiv = flsi(div >> 8); in atmel_i2c_init_clk()
238 cxdiv = div >> ckdiv; in atmel_i2c_init_clk()
/optee_os/core/drivers/
H A Dimx_i2c.c199 uint32_t div = (I2C_CLK_RATE + bps - 1) / bps; in i2c_set_prescaler() local
201 if (div < p->divider) in i2c_set_prescaler()
203 else if (div > q->divider) in i2c_set_prescaler()
207 if (div <= p->divider) in i2c_set_prescaler()
/optee_os/core/arch/arm/dts/
H A Dstm32mp257f-dk.dts78 st,tamp-passive-sample-clk-div = <16384>;
H A Dstm32mp235f-dk.dts70 st,tamp-passive-sample-clk-div = <16384>;
H A Dstm32mp257f-ev1.dts83 st,tamp-passive-sample-clk-div = <16384>;
H A Dstm32mp135f-dk.dts533 st,tamp-passive-sample-clk-div = <16384>;
H A Dstm32mp15xx-dkx.dtsi580 st,tamp-passive-sample-clk-div = <16384>;
/optee_os/core/arch/riscv/include/
H A Dencoding.h3432 DECLARE_INSN(div, MATCH_DIV, MASK_DIV)