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Searched refs:link_bw (Results 1 – 24 of 24) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/
H A Dnouveau_dp.c146 nv_encoder->dp.link_bw = 27000 * dpcd[DP_MAX_LINK_RATE]; in nouveau_dp_detect()
151 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, in nouveau_dp_detect()
155 nv_encoder->dcb->dpconf.link_bw); in nouveau_dp_detect()
159 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw) in nouveau_dp_detect()
160 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw; in nouveau_dp_detect()
163 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw); in nouveau_dp_detect()
244 max_rate = outp->dp.link_nr * outp->dp.link_bw; in nv50_dp_mode_valid()
H A Dnouveau_encoder.h67 int link_bw; member
H A Dnouveau_bios.c1474 entry->dpconf.link_bw = 162000; in parse_dcb20_entry()
1477 entry->dpconf.link_bw = 270000; in parse_dcb20_entry()
1480 entry->dpconf.link_bw = 540000; in parse_dcb20_entry()
1484 entry->dpconf.link_bw = 810000; in parse_dcb20_entry()
/OK3568_Linux_fs/u-boot/board/gdsys/common/
H A Ddp501.c53 u8 link_bw; in dp501_link_training() local
59 link_bw = 0x0a; in dp501_link_training()
61 link_bw = 0x06; in dp501_link_training()
62 if (link_bw != val) in dp501_link_training()
64 val * 270, link_bw * 270); in dp501_link_training()
65 i2c_reg_write(addr, 0x5d, link_bw); /* set link_bw */ in dp501_link_training()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c158 u8 link_bw, rate_select; in intel_dp_link_training_clock_recovery() local
164 &link_bw, &rate_select); in intel_dp_link_training_clock_recovery()
177 if (!link_bw) { in intel_dp_link_training_clock_recovery()
188 if (link_bw) in intel_dp_link_training_clock_recovery()
190 "Using LINK_BW_SET value %02x\n", link_bw); in intel_dp_link_training_clock_recovery()
196 link_config[0] = link_bw; in intel_dp_link_training_clock_recovery()
203 if (!link_bw) in intel_dp_link_training_clock_recovery()
H A Dintel_dp.h101 u8 *link_bw, u8 *rate_select);
H A Dintel_display.h543 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
H A Dintel_dp.c1943 u8 *link_bw, u8 *rate_select) in intel_dp_compute_rate() argument
1947 *link_bw = 0; in intel_dp_compute_rate()
1951 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); in intel_dp_compute_rate()
H A Dintel_display.c7902 int lane, link_bw, fdi_dotclock, ret; in ilk_fdi_compute_config() local
7913 link_bw = intel_fdi_link_freq(i915, pipe_config); in ilk_fdi_compute_config()
7917 lane = ilk_get_lanes_required(fdi_dotclock, link_bw, in ilk_fdi_compute_config()
7923 link_bw, &pipe_config->fdi_m_n, false, false); in ilk_fdi_compute_config()
10236 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) in ilk_get_lanes_required() argument
10244 return DIV_ROUND_UP(bps, link_bw * 8); in ilk_get_lanes_required()
/OK3568_Linux_fs/u-boot/drivers/video/tegra124/
H A Ddp.c432 link_cfg->link_bw); in tegra_dc_dp_dump_link_cfg()
455 switch (cfg->link_bw) { in _tegra_dp_lower_link_config()
458 cfg->link_bw = SOR_LINK_SPEED_G2_7; in _tegra_dp_lower_link_config()
462 cfg->link_bw = SOR_LINK_SPEED_G1_62; in _tegra_dp_lower_link_config()
466 cfg->link_bw = SOR_LINK_SPEED_G2_7; in _tegra_dp_lower_link_config()
473 debug("dp: Error link rate %d\n", cfg->link_bw); in _tegra_dp_lower_link_config()
488 const u32 link_rate = 27 * link_cfg->link_bw * 1000 * 1000; in tegra_dc_dp_calc_config()
711 link_cfg->link_bw = link_cfg->max_link_bw; in tegra_dc_dp_init_max_link_cfg()
740 u8 link_bw) in tegra_dp_set_link_bandwidth() argument
742 tegra_dc_sor_set_link_bandwidth(sor, link_bw); in tegra_dp_set_link_bandwidth()
[all …]
H A Dsor.c170 reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ? in tegra_dc_sor_set_dp_linkctl()
282 tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw); in tegra_dc_sor_set_dp_mode()
389 void tegra_dc_sor_read_link_config(struct udevice *dev, u8 *link_bw, in tegra_dc_sor_read_link_config() argument
396 *link_bw = (reg_val & CLK_CNTRL_DP_LINK_SPEED_MASK) in tegra_dc_sor_read_link_config()
419 void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw) in tegra_dc_sor_set_link_bandwidth() argument
425 link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT); in tegra_dc_sor_set_link_bandwidth()
845 tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw); in tegra_dc_sor_set_lane_parm()
869 switch (link_cfg->link_bw) { in tegra_dc_sor_set_voltage_swing()
878 debug("Invalid sor link bandwidth: %d\n", link_cfg->link_bw); in tegra_dc_sor_set_voltage_swing()
H A Dsor.h854 u8 link_bw; member
884 void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw);
889 void tegra_dc_sor_read_link_config(struct udevice *dev, u8 *link_bw,
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Ddcb.c147 outp->dpconf.link_bw = 0x06; in dcb_outp_parse()
150 outp->dpconf.link_bw = 0x0a; in dcb_outp_parse()
153 outp->dpconf.link_bw = 0x14; in dcb_outp_parse()
157 outp->dpconf.link_bw = 0x1e; in dcb_outp_parse()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Danx9805.c193 int link_nr, int link_bw, bool enh) in anx9805_aux_lnk_ctl() argument
201 link_nr, link_bw, enh); in anx9805_aux_lnk_ctl()
203 nvkm_wri2cr(adap, aux->addr, 0xa0, link_bw); in anx9805_aux_lnk_ctl()
H A Daux.h10 int (*lnk_ctl)(struct nvkm_i2c_aux *, int link_nr, int link_bw,
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Ddrm_dp_helper.c154 int drm_dp_bw_code_to_link_rate(u8 link_bw) in drm_dp_bw_code_to_link_rate() argument
156 switch (link_bw) { in drm_dp_bw_code_to_link_rate()
158 WARN(1, "unknown DP link BW code %x, using 162000\n", link_bw); in drm_dp_bw_code_to_link_rate()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c265 uint8_t link_bw; member
360 cdv_intel_dp_link_clock(uint8_t link_bw) in cdv_intel_dp_link_clock() argument
362 if (link_bw == DP_LINK_BW_2_7) in cdv_intel_dp_link_clock()
920 intel_dp->link_bw = bws[clock]; in cdv_intel_dp_mode_fixup()
922 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); in cdv_intel_dp_mode_fixup()
925 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
934 intel_dp->link_bw = bws[max_clock]; in cdv_intel_dp_mode_fixup()
935 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); in cdv_intel_dp_mode_fixup()
938 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
1074 intel_dp->link_configuration[0] = intel_dp->link_bw; in cdv_intel_dp_mode_set()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Ddcb.h49 int link_bw; member
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Di2c.h71 int nvkm_i2c_aux_lnk_ctl(struct nvkm_i2c_aux *, int link_nr, int link_bw,
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_link_dp.c2378 uint32_t link_bw; in decide_dp_link_settings() local
2389 link_bw = dc_link_bandwidth_kbps( in decide_dp_link_settings()
2392 if (req_bw <= link_bw) { in decide_dp_link_settings()
2418 uint32_t link_bw; in decide_edp_link_settings() local
2440 link_bw = dc_link_bandwidth_kbps( in decide_edp_link_settings()
2443 if (req_bw <= link_bw) { in decide_edp_link_settings()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/
H A Ddrm_dp_helper.c178 int drm_dp_bw_code_to_link_rate(u8 link_bw) in drm_dp_bw_code_to_link_rate() argument
181 return link_bw * 27000; in drm_dp_bw_code_to_link_rate()
/OK3568_Linux_fs/u-boot/include/drm/
H A Ddrm_dp_helper.h1023 int drm_dp_bw_code_to_link_rate(u8 link_bw);
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddp.c351 const u8 outp_bw = dp->outp.info.dpconf.link_bw; in nvkm_dp_train()
/OK3568_Linux_fs/kernel/include/drm/
H A Ddrm_dp_helper.h1193 int drm_dp_bw_code_to_link_rate(u8 link_bw);