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Searched refs:MV_OK (Results 1 – 25 of 31) sorted by relevance

12

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c197 if (MV_OK != ddr3_dfs_high_2_low(freq, &dram_info)) { in ddr3_hw_training()
205 if (MV_OK != in ddr3_hw_training()
230 if (MV_OK != in ddr3_hw_training()
238 if (MV_OK != in ddr3_hw_training()
246 if (MV_OK != ddr3_write_leveling_hw( in ddr3_hw_training()
250 if (MV_OK != in ddr3_hw_training()
268 if (MV_OK != ddr3_load_patterns(&dram_info, 0)) { in ddr3_hw_training()
300 if (MV_OK != ddr3_dfs_low_2_high(freq, tmp_ratio, in ddr3_hw_training()
321 if (MV_OK != ddr3_write_leveling_sw( in ddr3_hw_training()
327 if (MV_OK != ddr3_write_leveling_hw( in ddr3_hw_training()
[all …]
H A Dxor.c152 return MV_OK; in mv_xor_ctrl_set()
206 return MV_OK; in mv_xor_mem_init()
317 return MV_OK; in mv_xor_transfer()
407 return MV_OK; in mv_xor_cmd_set()
413 return MV_OK; in mv_xor_cmd_set()
419 return MV_OK; in mv_xor_cmd_set()
425 return MV_OK; in mv_xor_cmd_set()
429 return MV_OK; in mv_xor_cmd_set()
H A Dddr3_dqs.c174 if (MV_OK != status) in ddr3_dqs_centralization_rx()
181 if (MV_OK != status) in ddr3_dqs_centralization_rx()
203 return MV_OK; in ddr3_dqs_centralization_rx()
254 if (MV_OK != status) in ddr3_dqs_centralization_tx()
261 if (MV_OK != status) in ddr3_dqs_centralization_tx()
283 return MV_OK; in ddr3_dqs_centralization_tx()
413 if (MV_OK != ddr3_sdram_dqs_compare(dram_info, in ddr3_find_adll_limits()
508 if (MV_OK != in ddr3_find_adll_limits()
815 return MV_OK; in ddr3_find_adll_limits()
839 return MV_OK; in ddr3_check_window_limits()
[all …]
H A Dddr3_pbs.c218 if (MV_OK != ddr3_tx_shift_dqs_adll_step_before_fail in ddr3_pbs_tx()
229 if (MV_OK != ddr3_pbs_per_bit( in ddr3_pbs_tx()
393 return MV_OK; in ddr3_pbs_tx()
463 if (MV_OK != ddr3_sdram_compare(dram_info, unlock_pup, in ddr3_tx_shift_dqs_adll_step_before_fail()
510 return MV_OK; in ddr3_tx_shift_dqs_adll_step_before_fail()
668 if (MV_OK != status) { in ddr3_pbs_rx()
723 return MV_OK; in ddr3_pbs_rx()
729 if (MV_OK != ddr3_pbs_per_bit( in ddr3_pbs_rx()
905 return MV_OK; in ddr3_pbs_rx()
966 if (MV_OK != ddr3_sdram_compare(dram_info, unlock_pup, in ddr3_rx_shift_dqs_to_first_fail()
[all …]
H A Dddr3_sdram.c201 return MV_OK; in ddr3_sdram_compare()
265 return MV_OK; in ddr3_sdram_dm_compare()
423 return MV_OK; in ddr3_sdram_pbs_compare()
482 return MV_OK; in ddr3_sdram_direct_compare()
537 if (mv_xor_transfer(chan, MV_DMA, channel.desc_phys_addr) != MV_OK) in ddr3_dram_sram_burst()
548 return MV_OK; in ddr3_dram_sram_burst()
597 return MV_OK; in ddr3_dram_sram_read()
634 return MV_OK; in ddr3_sdram_dqs_compare()
H A Dddr3_write_leveling.c171 return MV_OK; in ddr3_write_leveling_hw()
267 if (MV_OK != ddr3_dram_sram_burst((u32) in ddr3_wl_supplement()
274 if (MV_OK != in ddr3_wl_supplement()
462 return MV_OK; in ddr3_wl_supplement()
616 return MV_OK; in ddr3_write_leveling_hw_reg_dimm()
768 if (MV_OK != in ddr3_write_leveling_sw()
870 return MV_OK; in ddr3_write_leveling_sw()
1009 if (MV_OK != in ddr3_write_leveling_sw_reg_dimm()
1111 return MV_OK; in ddr3_write_leveling_sw_reg_dimm()
1333 return MV_OK; in ddr3_write_leveling_single_cs()
H A Dddr3_spd.c496 return MV_OK; in ddr3_spd_init()
511 return MV_OK; in ddr3_spd_sum_init()
565 return MV_OK; in ddr3_spd_sum_init()
600 if (MV_OK != status)
608 if (MV_OK != status)
629 if (MV_OK != status)
632 if (MV_OK != status)
1239 return MV_OK;
H A Dddr3_read_leveling.c164 return MV_OK; in ddr3_read_leveling_hw()
249 if (MV_OK != status) in ddr3_read_leveling_sw()
257 if (MV_OK != status) in ddr3_read_leveling_sw()
328 return MV_OK; in ddr3_read_leveling_sw()
459 if (MV_OK != in ddr3_read_leveling_single_cs_rl_mode()
737 return MV_OK; in ddr3_read_leveling_single_cs_rl_mode()
813 if (MV_OK != in ddr3_read_leveling_single_cs_window_mode()
1212 return MV_OK; in ddr3_read_leveling_single_cs_window_mode()
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_hws_hw_training.c64 return MV_OK; in ddr3_pre_algo_config()
73 if (MV_OK != status) { in ddr3_post_algo_config()
88 return MV_OK; in ddr3_post_algo_config()
98 if (MV_OK != status) { in ddr3_hws_hw_training()
117 if (MV_OK != status) { in ddr3_hws_hw_training()
123 if (MV_OK != status) { in ddr3_hws_hw_training()
129 if (MV_OK != status) { in ddr3_hws_hw_training()
136 if (MV_OK != status) { in ddr3_hws_hw_training()
142 if (MV_OK != status) { in ddr3_hws_hw_training()
147 return MV_OK; in ddr3_hws_hw_training()
H A Dddr3_a38x.c246 return MV_OK; in ddr3_tip_a38x_get_freq_config()
275 return MV_OK; in ddr3_tip_a38x_pipe_enable()
300 return MV_OK; in ddr3_tip_a38x_if_write()
315 return MV_OK; in ddr3_tip_a38x_if_read()
339 return MV_OK; in ddr3_tip_a38x_select_ddr_controller()
388 if (MV_OK != status) { in ddr3_tip_init_a38x_silicon()
445 return MV_OK; in ddr3_tip_init_a38x_silicon()
462 return MV_OK; in ddr3_a38x_update_topology_map()
475 return MV_OK; in ddr3_tip_init_a38x()
526 return MV_OK; in ddr3_tip_a38x_get_init_freq()
[all …]
H A Dddr3_training.c201 return MV_OK; in ddr3_tip_tune_training_params()
257 return MV_OK; in ddr3_tip_configure_cs()
294 return MV_OK; in calc_cs_num()
665 return MV_OK; in hws_ddr3_tip_init_controller()
717 return MV_OK; in hws_ddr3_tip_load_topology_map()
752 return MV_OK; in ddr3_tip_rank_control()
793 return MV_OK; in ddr3_tip_pad_inv()
801 int ret = MV_OK, ret_tune = MV_OK; in hws_ddr3_tip_run_alg()
832 if (ret != MV_OK) { in hws_ddr3_tip_run_alg()
846 int ret = MV_OK, ret_tune = MV_OK; in odt_test()
[all …]
H A Dddr3_training_bist.c134 return MV_OK; in ddr3_tip_bist_activate()
155 if (ret != MV_OK) in ddr3_tip_bist_read_result()
161 if (ret != MV_OK) in ddr3_tip_bist_read_result()
168 if (ret != MV_OK) in ddr3_tip_bist_read_result()
174 if (ret != MV_OK) in ddr3_tip_bist_read_result()
178 return MV_OK; in ddr3_tip_bist_read_result()
202 if (ret != MV_OK) { in hws_ddr3_run_bist()
213 if (ret != MV_OK) { in hws_ddr3_run_bist()
219 if (ret != MV_OK) { in hws_ddr3_run_bist()
226 return MV_OK; in hws_ddr3_run_bist()
[all …]
H A Dddr3_training_leveling.c103 MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_dynamic_read_leveling()
147 return MV_OK; in ddr3_tip_dynamic_read_leveling()
287 MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_dynamic_read_leveling()
314 ODPG_ENABLE_REG, MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_dynamic_read_leveling()
336 MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_dynamic_read_leveling()
435 return MV_OK; in ddr3_tip_dynamic_read_leveling()
469 MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_legacy_dynamic_write_leveling()
476 return MV_OK; in ddr3_tip_legacy_dynamic_write_leveling()
510 MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_legacy_dynamic_read_leveling()
517 return MV_OK; in ddr3_tip_legacy_dynamic_read_leveling()
[all …]
H A Dddr3_init.c195 if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK) in ddr3_restore_and_set_final_windows()
279 return MV_OK; in ddr3_save_and_set_training_windows()
335 return MV_OK; in ddr3_init()
385 if (MV_OK != status) in ddr3_init()
393 if (MV_OK != status) { in ddr3_init()
419 return MV_OK; in ddr3_init()
596 if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK) in ddr3_fast_path_dynamic_cs_size_config()
657 return MV_OK; in ddr3_fast_path_dynamic_cs_size_config()
740 return MV_OK; in ddr3_calc_mem_cs_size()
763 if (MV_OK != status) { in ddr3_hws_tune_training_params()
[all …]
H A Dxor.c154 return MV_OK; in mv_xor_ctrl_set()
208 return MV_OK; in mv_xor_mem_init()
297 return MV_OK; in mv_xor_command_set()
303 return MV_OK; in mv_xor_command_set()
310 return MV_OK; in mv_xor_command_set()
316 return MV_OK; in mv_xor_command_set()
319 return MV_OK; in mv_xor_command_set()
H A Dddr3_a38x_training.c29 return MV_OK; in ddr3_silicon_init()
32 if (MV_OK != status) { in ddr3_silicon_init()
39 return MV_OK; in ddr3_silicon_init()
H A Dddr3_training_static.c71 return MV_OK; in ddr3_tip_init_specific_reg_config()
86 return MV_OK; in ddr3_tip_init_static_config_db()
142 return MV_OK; in ddr3_tip_static_round_trip_arr_build()
200 return MV_OK; in ddr3_tip_write_leveling_static_config()
337 return MV_OK; in ddr3_tip_read_leveling_static_config()
360 if (ret != MV_OK) { in ddr3_tip_run_static_alg()
394 return MV_OK; in ddr3_tip_run_static_alg()
423 return MV_OK; in ddr3_tip_static_init_controller()
463 return MV_OK; in ddr3_tip_static_phy_init_controller()
537 return MV_OK; in ddr3_tip_configure_phy()
H A Dddr3_training_ip_engine.c472 return MV_OK; in ddr3_tip_ip_training()
511 return MV_OK; in ddr3_tip_load_pattern_to_odpg()
532 if (ret != MV_OK) in ddr3_tip_configure_odpg()
535 return MV_OK; in ddr3_tip_configure_odpg()
578 return MV_OK; in ddr3_tip_process_result()
732 return MV_OK; in ddr3_tip_read_training_result()
759 return MV_OK; in ddr3_tip_load_all_pattern_to_mem()
792 return MV_OK; in is_odpg_access_done()
871 return MV_OK; in ddr3_tip_load_pattern_to_mem()
881 return MV_OK; in ddr3_tip_load_pattern_to_mem_by_cpu()
[all …]
H A Dddr3_debug.c149 return MV_OK; in ddr3_tip_reg_dump()
164 return MV_OK; in ddr3_tip_init_config_func()
292 return MV_OK; in print_device_info()
480 return MV_OK; in ddr3_tip_print_log()
641 return MV_OK; in ddr3_tip_print_stability_log()
650 return MV_OK; in ddr3_tip_register_xsb_info()
789 return MV_OK; in ddr3_tip_print_adll()
1157 return MV_OK; in ddr3_tip_access_atr()
1178 return MV_OK; in print_adll()
1275 return MV_OK; in ddr3_tip_sweep_test()
[all …]
H A Dddr3_training_centralization.c42 return MV_OK; in ddr3_tip_centralization_rx()
52 return MV_OK; in ddr3_tip_centralization_tx()
515 return MV_OK; in ddr3_tip_special_rx()
689 return MV_OK; in ddr3_tip_special_rx()
711 return MV_OK; in ddr3_tip_print_centralization_result()
/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dseq_exec.c41 return MV_OK; in write_op_execute()
67 return MV_OK; in write_op_execute()
81 return MV_OK; in delay_op_execute()
98 return MV_OK; in poll_op_execute()
124 return MV_OK; in poll_op_execute()
168 return MV_OK; in mv_seq_exec()
H A Dhigh_speed_env_spec.c860 return MV_OK; in hws_serdes_topology_verify()
1293 return MV_OK; in hws_serdes_seq_db_init()
1408 return MV_OK; in hws_pre_serdes_init_config()
1423 if (hws_serdes_seq_init() != MV_OK) { in serdes_phy_config()
1452 return MV_OK; in serdes_phy_config()
1466 return MV_OK; in serdes_polarity_config()
1553 return MV_OK; in hws_power_up_serdes_lanes()
1585 return MV_OK; in serdes_pex_usb3_pipe_delay_w_a()
1636 return MV_OK; in hws_serdes_pex_ref_clock_satr_get()
1908 return MV_OK; in serdes_power_up_ctrl()
[all …]
H A Dhigh_speed_env_spec-38x.c40 if (hws_serdes_seq_db_init() != MV_OK) { in hws_serdes_seq_init()
45 return MV_OK; in hws_serdes_seq_init()
116 return MV_OK; in hws_get_ext_base_addr()
H A Dctrl_pex.c225 return MV_OK; in hws_pex_config()
246 return MV_OK; in pex_local_bus_num_set()
261 return MV_OK; in pex_local_dev_num_set()
/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c147 return MV_OK; in board_modules_scan()
249 int status = MV_OK; in serdes_phy_config()
274 return MV_OK; in serdes_phy_config()
290 return MV_OK; in serdes_phy_config()
939 status = MV_OK; in serdes_phy_config()
997 if (status == MV_OK) in serdes_phy_config()
1416 return MV_OK; in serdes_phy_config()
1575 return MV_OK; in pex_local_bus_num_set()
1610 return MV_OK; in pex_local_dev_num_set()

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