Searched refs:INT_SEL (Results 1 – 17 of 17) sorted by relevance
195 #define INT_SEL(x) ((x) << 24) macro
256 #define INT_SEL(x) ((x) << 24) macro
374 #define INT_SEL(x) ((x) << 24) macro
2195 DATA_SEL(1) | INT_SEL(0)); in gfx_v7_0_ring_emit_fence_gfx()2207 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_gfx()2234 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
1832 #define INT_SEL(x) ((x) << 24) macro
6196 DATA_SEL(1) | INT_SEL(0)); in gfx_v8_0_ring_emit_fence_gfx()6210 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_gfx()6287 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_compute()
5355 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_0_ring_emit_fence()
52 #define INT_SEL BIT(10) macro
2180 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV)); in _nbu2ss_enable_controller()
1255 #define INT_SEL(x) ((x) << 24) macro
1769 #define INT_SEL(x) ((x) << 24) macro
1842 #define INT_SEL(x) ((x) << 24) macro
1680 #define INT_SEL(x) ((x) << 24) macro
1420 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in cayman_fence_ring_emit()
3566 DATA_SEL(1) | INT_SEL(0)); in cik_fence_gfx_ring_emit()3577 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); in cik_fence_gfx_ring_emit()3603 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); in cik_fence_compute_ring_emit()
2888 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in r600_fence_ring_emit()
3396 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in si_fence_ring_emit()