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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/
H A Dbrcm,bcm7120-l2-intc.txt4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
24 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
32 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
38 7 ---------------------|---|===========> GIC interrupt 66
44 |===========> GIC interrupt 64
H A Dmarvell,gicp.txt4 GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
7 into GIC SPI interrupts.
15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
H A Dqcom,pdc.txt7 well detect interrupts when the GIC is non-operational.
9 GIC is parent interrupt controller at the highest level. Platform interrupt
13 with the GIC interrupt. See example below.
28 Optionally, specify the PDC's GIC interface registers that
54 The second element is the GIC hwirq number for the PDC port.
62 register to the GIC can only be written from the firmware.
76 DT binding of a device that wants to use the GIC SPI 514 as a wakeup
H A Dti,omap4-wugen-mpu4 routes interrupts to the GIC, and also serves as a wakeup source. It
18 - Because this HW ultimately routes interrupts to the GIC, the
19 interrupt specifier must be that of the GIC.
H A Dmediatek,cirq.txt4 work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC.
6 to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
18 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
H A Dnvidia,tegra20-ictlr.txt4 interrupts to the GIC, and also serves as a wakeup source. It is also
25 - Because this HW ultimately routes interrupts to the GIC, the
26 interrupt specifier must be that of the GIC.
H A Dmarvell,icu.txt6 communicating them to the GIC in the AP, the unit translates interrupt
7 requests on input wires to MSG memory mapped transactions to the GIC.
8 These messages will access a different GIC memory area depending on
39 - msi-parent: Should point to the GICP controller, the GIC extension
H A Dmarvell,armada-8k-pic.txt6 typically connected to the GIC as the primary interrupt controller.
15 typically the GIC
H A Dmarvell,odmi-controller.txt23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
27 for details about the GIC Device Tree binding.
H A Dmarvell,armada-370-xp-mpic.txt24 connected as a slave to the Cortex-A9 GIC. The provided interrupt
25 indicate to which GIC interrupt the MPIC output is connected.
H A Dmediatek,sysirq.txt3 MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
29 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
H A Dfsl,ls-scfg-msi.txt17 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
H A Dfsl,ls-extirq.txt17 - interrupt-map: Specifies the mapping from external interrupts to GIC
/OK3568_Linux_fs/kernel/drivers/net/ethernet/renesas/
H A Dravb_ptp.c201 ravb_modify(ndev, GIC, GIC_PTCE, on ? GIC_PTCE : 0); in ravb_ptp_extts()
256 ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME); in ravb_ptp_perout()
268 ravb_modify(ndev, GIC, GIC_PTME, 0); in ravb_ptp_perout()
309 gis &= ravb_read(ndev, GIC); in ravb_ptp_interrupt()
352 ravb_write(ndev, 0, GIC); in ravb_ptp_stop()
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/mti/
H A Dsead3.dts64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
253 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
/OK3568_Linux_fs/kernel/Documentation/virt/kvm/devices/
H A Darm-vgic.rst27 Base address in the guest physical address space of the GIC distributor
32 Base address in the guest physical address space of the GIC virtual cpu
110 a GIC without the security extensions expose group 0 and group 1 active
132 this GIC instance, ranging from 64 to 1024, in increments of 32.
138 -EBUSY Value has already be set, or GIC has already been initialized
H A Dvcpu.rst51 -ENODEV PMUv3 not supported or GIC not initialized
58 virtual GIC implementation, this must be done after initializing the in-kernel
70 -ENODEV PMUv3 not supported or GIC not initialized
127 in-kernel virtual GIC. These must be a PPI (16 <= intid < 32). Setting the
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/freescale/
H A Dfsl,vf610-mscm-ir.txt19 Flags get passed only when using GIC as parent. Flags
20 encoding as documented by the GIC bindings.
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S124 add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset
130 movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
131 moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Darm-realview-eb.dts34 * This is the core tile with the CPU and GIC etc for the
64 * to the GIC on the core tile.
H A Darm-realview-eb-mp.dtsi119 * to the GIC on the core tile.
181 * GIC.
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.txt38 For GICv3 and GIC ITS bindings, see:
127 - msi-map: Maps an ICID to a GIC ITS and associated msi-specifier
134 associated with the listed GIC ITS, with the msi-specifier
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/omap/
H A Dmpu.txt5 The MPU contain CPUs, GIC, L2 cache and a local PRCM.
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/timer/
H A Darm,twd.txt7 The TWD is usually attached to a GIC to deliver its two per-processor
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/apm/
H A Dapm-shadowcat.dtsi118 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
120 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
121 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
122 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
123 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */

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