1*4882a593Smuzhiyun* Freescale Layerscape external IRQs 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunSome Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting 4*4882a593Smuzhiyunthe polarity of certain external interrupt lines. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThe device node must be a child of the node representing the 7*4882a593SmuzhiyunSupplemental Configuration Unit (SCFG). 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq". 11*4882a593Smuzhiyun- #interrupt-cells: Must be 2. The first element is the index of the 12*4882a593Smuzhiyun external interrupt line. The second element is the trigger type. 13*4882a593Smuzhiyun- #address-cells: Must be 0. 14*4882a593Smuzhiyun- interrupt-controller: Identifies the node as an interrupt controller 15*4882a593Smuzhiyun- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in 16*4882a593Smuzhiyun the SCFG. 17*4882a593Smuzhiyun- interrupt-map: Specifies the mapping from external interrupts to GIC 18*4882a593Smuzhiyun interrupts. 19*4882a593Smuzhiyun- interrupt-map-mask: Must be <0xffffffff 0>. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun scfg: scfg@1570000 { 23*4882a593Smuzhiyun compatible = "fsl,ls1021a-scfg", "syscon"; 24*4882a593Smuzhiyun reg = <0x0 0x1570000 0x0 0x10000>; 25*4882a593Smuzhiyun big-endian; 26*4882a593Smuzhiyun #address-cells = <1>; 27*4882a593Smuzhiyun #size-cells = <1>; 28*4882a593Smuzhiyun ranges = <0x0 0x0 0x1570000 0x10000>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun extirq: interrupt-controller@1ac { 31*4882a593Smuzhiyun compatible = "fsl,ls1021a-extirq"; 32*4882a593Smuzhiyun #interrupt-cells = <2>; 33*4882a593Smuzhiyun #address-cells = <0>; 34*4882a593Smuzhiyun interrupt-controller; 35*4882a593Smuzhiyun reg = <0x1ac 4>; 36*4882a593Smuzhiyun interrupt-map = 37*4882a593Smuzhiyun <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 38*4882a593Smuzhiyun <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 39*4882a593Smuzhiyun <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 40*4882a593Smuzhiyun <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 41*4882a593Smuzhiyun <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 42*4882a593Smuzhiyun <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 43*4882a593Smuzhiyun interrupt-map-mask = <0xffffffff 0x0>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 49*4882a593Smuzhiyun <&extirq 1 IRQ_TYPE_LEVEL_LOW>; 50