1*4882a593Smuzhiyun* Freescale Layerscape SCFG PCIe MSI controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties:
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun- compatible: should be "fsl,<soc-name>-msi" to identify
6*4882a593Smuzhiyun	      Layerscape PCIe MSI controller block such as:
7*4882a593Smuzhiyun              "fsl,ls1021a-msi"
8*4882a593Smuzhiyun              "fsl,ls1043a-msi"
9*4882a593Smuzhiyun              "fsl,ls1046a-msi"
10*4882a593Smuzhiyun              "fsl,ls1043a-v1.1-msi"
11*4882a593Smuzhiyun              "fsl,ls1012a-msi"
12*4882a593Smuzhiyun- msi-controller: indicates that this is a PCIe MSI controller node
13*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped.
14*4882a593Smuzhiyun- interrupts: an interrupt to the parent interrupt controller.
15*4882a593Smuzhiyun
16*4882a593SmuzhiyunThis interrupt controller hardware is a second level interrupt controller that
17*4882a593Smuzhiyunis hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
18*4882a593Smuzhiyunplatforms. If interrupt-parent is not provided, the default parent interrupt
19*4882a593Smuzhiyuncontroller will be used.
20*4882a593SmuzhiyunEach PCIe node needs to have property msi-parent that points to
21*4882a593SmuzhiyunMSI controller node
22*4882a593Smuzhiyun
23*4882a593SmuzhiyunExamples:
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	msi1: msi-controller@1571000 {
26*4882a593Smuzhiyun		compatible = "fsl,ls1043a-msi";
27*4882a593Smuzhiyun		reg = <0x0 0x1571000 0x0 0x8>,
28*4882a593Smuzhiyun		msi-controller;
29*4882a593Smuzhiyun		interrupts = <0 116 0x4>;
30*4882a593Smuzhiyun	};
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