1*4882a593Smuzhiyun 2*4882a593Smuzhiyun* Marvell ODMI for MSI support 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunSome Marvell SoCs have an On-Die Message Interrupt (ODMI) controller 5*4882a593Smuzhiyunwhich can be used by on-board peripheral for MSI interrupts. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible : The value here should contain: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun "marvell,ap806-odmi-controller", "marvell,odmi-controller". 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- interrupt,controller : Identifies the node as an interrupt controller. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- msi-controller : Identifies the node as an MSI controller. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- marvell,odmi-frames : Number of ODMI frames available. Each frame 18*4882a593Smuzhiyun provides a number of events. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- reg : List of register definitions, one for each 21*4882a593Smuzhiyun ODMI frame. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- marvell,spi-base : List of GIC base SPI interrupts, one for each 24*4882a593Smuzhiyun ODMI frame. Those SPI interrupts are 0-based, 25*4882a593Smuzhiyun i.e marvell,spi-base = <128> will use SPI #96. 26*4882a593Smuzhiyun See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml 27*4882a593Smuzhiyun for details about the GIC Device Tree binding. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun odmi: odmi@300000 { 32*4882a593Smuzhiyun compatible = "marvell,ap806-odmi-controller", 33*4882a593Smuzhiyun "marvell,odmi-controller"; 34*4882a593Smuzhiyun interrupt-controller; 35*4882a593Smuzhiyun msi-controller; 36*4882a593Smuzhiyun marvell,odmi-frames = <4>; 37*4882a593Smuzhiyun reg = <0x300000 0x4000>, 38*4882a593Smuzhiyun <0x304000 0x4000>, 39*4882a593Smuzhiyun <0x308000 0x4000>, 40*4882a593Smuzhiyun <0x30C000 0x4000>; 41*4882a593Smuzhiyun marvell,spi-base = <128>, <136>, <144>, <152>; 42*4882a593Smuzhiyun }; 43