1*4882a593SmuzhiyunFreescale Vybrid Miscellaneous System Control - Interrupt Router 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe MSCM IP contains multiple sub modules, this binding describes the second 4*4882a593Smuzhiyunblock of registers which control the interrupt router. The interrupt router 5*4882a593Smuzhiyunallows to configure the recipient of each peripheral interrupt. Furthermore 6*4882a593Smuzhiyunit controls the directed processor interrupts. The module is available in all 7*4882a593SmuzhiyunVybrid SoC's but is only really useful in dual core configurations (VF6xx 8*4882a593Smuzhiyunwhich comes with a Cortex-A5/Cortex-M4 combination). 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible: "fsl,vf610-mscm-ir" 12*4882a593Smuzhiyun- reg: the register range of the MSCM Interrupt Router 13*4882a593Smuzhiyun- fsl,cpucfg: The handle to the MSCM CPU configuration node, required 14*4882a593Smuzhiyun to get the current CPU ID 15*4882a593Smuzhiyun- interrupt-controller: Identifies the node as an interrupt controller 16*4882a593Smuzhiyun- #interrupt-cells: Two cells, interrupt number and cells. 17*4882a593Smuzhiyun The hardware interrupt number according to interrupt 18*4882a593Smuzhiyun assignment of the interrupt router is required. 19*4882a593Smuzhiyun Flags get passed only when using GIC as parent. Flags 20*4882a593Smuzhiyun encoding as documented by the GIC bindings. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun mscm_ir: interrupt-controller@40001800 { 24*4882a593Smuzhiyun compatible = "fsl,vf610-mscm-ir"; 25*4882a593Smuzhiyun reg = <0x40001800 0x400>; 26*4882a593Smuzhiyun fsl,cpucfg = <&mscm_cpucfg>; 27*4882a593Smuzhiyun interrupt-controller; 28*4882a593Smuzhiyun #interrupt-cells = <2>; 29*4882a593Smuzhiyun interrupt-parent = <&intc>; 30*4882a593Smuzhiyun } 31