1*4882a593SmuzhiyunMarvell Armada 370, 375, 38x, XP Interrupt Controller
2*4882a593Smuzhiyun-----------------------------------------------------
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunRequired properties:
5*4882a593Smuzhiyun- compatible: Should be "marvell,mpic"
6*4882a593Smuzhiyun- interrupt-controller: Identifies the node as an interrupt controller.
7*4882a593Smuzhiyun- msi-controller: Identifies the node as an PCI Message Signaled
8*4882a593Smuzhiyun  Interrupt controller.
9*4882a593Smuzhiyun- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
10*4882a593Smuzhiyun  The cell is the IRQ number
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun- reg: Should contain PMIC registers location and length. First pair
13*4882a593Smuzhiyun  for the main interrupt registers, second pair for the per-CPU
14*4882a593Smuzhiyun  interrupt registers. For this last pair, to be compliant with SMP
15*4882a593Smuzhiyun  support, the "virtual" must be use (For the record, these registers
16*4882a593Smuzhiyun  automatically map to the interrupt controller registers of the
17*4882a593Smuzhiyun  current CPU)
18*4882a593Smuzhiyun
19*4882a593SmuzhiyunOptional properties:
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun- interrupts: If defined, then it indicates that this MPIC is
22*4882a593Smuzhiyun  connected as a slave to another interrupt controller. This is
23*4882a593Smuzhiyun  typically the case on Armada 375 and Armada 38x, where the MPIC is
24*4882a593Smuzhiyun  connected as a slave to the Cortex-A9 GIC. The provided interrupt
25*4882a593Smuzhiyun  indicate to which GIC interrupt the MPIC output is connected.
26*4882a593Smuzhiyun
27*4882a593SmuzhiyunExample:
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun        mpic: interrupt-controller@d0020000 {
30*4882a593Smuzhiyun              compatible = "marvell,mpic";
31*4882a593Smuzhiyun              #interrupt-cells = <1>;
32*4882a593Smuzhiyun              #address-cells = <1>;
33*4882a593Smuzhiyun              #size-cells = <1>;
34*4882a593Smuzhiyun              interrupt-controller;
35*4882a593Smuzhiyun              msi-controller;
36*4882a593Smuzhiyun              reg = <0xd0020a00 0x1d0>,
37*4882a593Smuzhiyun                    <0xd0021070 0x58>;
38*4882a593Smuzhiyun        };
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