Searched hist:"5 e0be8c0241e5075b34bd5b14df2df9f048715d3" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/drivers/st/ |
| H A D | stm32mp2_ddr_helpers.h | 5e0be8c0241e5075b34bd5b14df2df9f048715d3 Tue May 21 18:54:04 UTC 2024 Yann Gautier <yann.gautier@st.com> feat(stm32mp2): enable DDR sub-system clock
Create a DDR helper files, and add a function to enable DDR clocks
in RCC_DDRCPCFGR register.
Call this ddr_sub_system_clk_init() just before clock driver init,
as it needs to be done before enabling DDR PLL clock (PLL2).
Change-Id: I365d6aa034363d0c036ce2d9f944f077ba86e193
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| /rk3399_ARM-atf/drivers/st/ddr/ |
| H A D | stm32mp2_ddr_helpers.c | 5e0be8c0241e5075b34bd5b14df2df9f048715d3 Tue May 21 18:54:04 UTC 2024 Yann Gautier <yann.gautier@st.com> feat(stm32mp2): enable DDR sub-system clock
Create a DDR helper files, and add a function to enable DDR clocks
in RCC_DDRCPCFGR register.
Call this ddr_sub_system_clk_init() just before clock driver init,
as it needs to be done before enabling DDR PLL clock (PLL2).
Change-Id: I365d6aa034363d0c036ce2d9f944f077ba86e193
Signed-off-by: Yann Gautier <yann.gautier@st.com>
|
| /rk3399_ARM-atf/plat/st/stm32mp2/ |
| H A D | bl2_plat_setup.c | 5e0be8c0241e5075b34bd5b14df2df9f048715d3 Tue May 21 18:54:04 UTC 2024 Yann Gautier <yann.gautier@st.com> feat(stm32mp2): enable DDR sub-system clock
Create a DDR helper files, and add a function to enable DDR clocks
in RCC_DDRCPCFGR register.
Call this ddr_sub_system_clk_init() just before clock driver init,
as it needs to be done before enabling DDR PLL clock (PLL2).
Change-Id: I365d6aa034363d0c036ce2d9f944f077ba86e193
Signed-off-by: Yann Gautier <yann.gautier@st.com>
|
| H A D | platform.mk | 5e0be8c0241e5075b34bd5b14df2df9f048715d3 Tue May 21 18:54:04 UTC 2024 Yann Gautier <yann.gautier@st.com> feat(stm32mp2): enable DDR sub-system clock
Create a DDR helper files, and add a function to enable DDR clocks
in RCC_DDRCPCFGR register.
Call this ddr_sub_system_clk_init() just before clock driver init,
as it needs to be done before enabling DDR PLL clock (PLL2).
Change-Id: I365d6aa034363d0c036ce2d9f944f077ba86e193
Signed-off-by: Yann Gautier <yann.gautier@st.com>
|