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/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Dcpm2.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * All CPM control and status is available through the CPM2 internal
27 /* Device sub-block and page codes.
72 /* CPM2-specific opcodes (see cpm.h for common opcodes)
113 * oversampled clock.
157 * get some microcode patches :-).
158 * The parameter ram space for the SMCs is fifty-some bytes, and
165 /* Define enough so I can at least use the serial port as a UART.
173 uint smc_rstate; /* Internal */
174 uint smc_idp; /* Internal */
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H A Dcpm1.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * through the MPC8xx internal memory map. See immap.h for details.
11 * are needed. -- Dan
13 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
16 * or other use.
75 /* Define enough so I can at least use the serial port as a UART.
84 uint smc_rstate; /* Internal */
85 uint smc_idp; /* Internal */
86 ushort smc_rbptr; /* Internal */
87 ushort smc_ibc; /* Internal */
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/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dcpm_85xx.h11 * All CPM control and status is available through the MPC8260 internal
28 /* Device sub-block and page codes.
73 * any CPM use, so we put the BDs there. The first 128 bytes are
82 #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
85 #define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
131 #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
132 #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
260 uint scc_rstate; /* Internal */
261 uint scc_idp; /* Internal */
262 ushort scc_rbptr; /* Internal */
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/OK3568_Linux_fs/kernel/Documentation/sound/cards/
H A Dhdspm.rst2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
24 use for a lower number of channels is only resource allocation,
29 * Single Speed -- 1..64 channels
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
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/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Domap_hwmod.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2011-2012 Texas Instruments, Inc.
13 * These headers and macros are used to define OMAP on-chip module
16 * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
20 * - add interconnect error log structures
21 * - init_conn_id_bit (CONNID_BIT_VECTOR)
22 * - implement default hwmod SMS/SDRC flags?
23 * - move Linux-specific data ("non-ROM data") out
155 * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
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H A Dmsdi.c1 // SPDX-License-Identifier: GPL-2.0-only
32 /* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
36 * omap_msdi_reset - reset the MSDI IP block
41 * successfully. This is not documented in the TRM. For CLKD, we use
42 * the value that results in the lowest possible clock rate, to attempt
53 /* Enable the MSDI core and internal clock */ in omap_msdi_reset()
59 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) in omap_msdi_reset()
65 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); in omap_msdi_reset()
68 oh->name, c); in omap_msdi_reset()
70 /* Disable the MSDI internal clock */ in omap_msdi_reset()
/OK3568_Linux_fs/kernel/Documentation/core-api/
H A Dkernel-api.rst9 .. kernel-doc:: include/linux/list.h
10 :internal:
15 When writing drivers, you cannot in general use routines which are from
22 ------------------
24 .. kernel-doc:: lib/vsprintf.c
27 .. kernel-doc:: include/linux/kernel.h
30 .. kernel-doc:: include/linux/kernel.h
33 .. kernel-doc:: lib/kstrtox.c
36 .. kernel-doc:: lib/string_helpers.c
40 -------------------
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 ti,min-output-impedance:
40 ti,max-output-impedance:
45 Note: ti,min-output-impedance and ti,max-output-impedance are mutually
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Drenesas,fsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas FIFO-buffered Serial Interface (FSI)
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
19 - items:
20 - enum:
21 - renesas,fsi2-sh73a0 # SH-Mobile AG5
22 - renesas,fsi2-r8a7740 # R-Mobile A1
23 - enum:
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/OK3568_Linux_fs/kernel/include/linux/platform_data/
H A Dad7793.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * enum ad7793_clock_source - AD7793 clock source selection
12 * @AD7793_CLK_SRC_INT: Internal 64 kHz clock, not available at the CLK pin.
13 * @AD7793_CLK_SRC_INT_CO: Internal 64 kHz clock, available at the CLK pin.
14 * @AD7793_CLK_SRC_EXT: Use external clock.
15 * @AD7793_CLK_SRC_EXT_DIV2: Use external clock divided by 2.
25 * enum ad7793_bias_voltage - AD7793 bias voltage selection
27 * @AD7793_BIAS_VOLTAGE_AIN1: Bias voltage connected to AIN1(-).
28 * @AD7793_BIAS_VOLTAGE_AIN2: Bias voltage connected to AIN2(-).
29 * @AD7793_BIAS_VOLTAGE_AIN3: Bias voltage connected to AIN3(-).
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/OK3568_Linux_fs/kernel/Documentation/driver-api/media/
H A Dcamera-sensor.rst1 .. SPDX-License-Identifier: GPL-2.0
6 CSI-2
7 -----
12 ---------------
14 Camera sensors have an internal clock tree including a PLL and a number of
15 divisors. The clock tree is generally configured by the driver based on a few
16 input parameters that are specific to the hardware:: the external clock frequency
20 The reason why the clock frequencies are so important is that the clock signals
23 elsewhere. Therefore only the pre-determined frequencies are configurable by the
27 ----------
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/OK3568_Linux_fs/kernel/include/linux/
H A Dtimekeeper_internal.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * handling code or timekeeping internal code!
15 * struct tk_read_base - base structure for timekeeping readout
16 * @clock: Current clocksource used for timekeeping.
18 * @cycle_last: @clock cycle value at last update
23 * @base_real: Nanoseconds base value for clock REALTIME readout
31 * @base_real is for the fast NMI safe accessor to allow reading clock
35 struct clocksource *clock; member
46 * struct timekeeper - Structure holding internal timekeeping values.
52 * @offs_real: Offset clock monotonic -> clock realtime
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/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-a20-gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
21 * This clock looks something like this
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/imu/
H A Dadi,adis16480.txt6 - compatible: Must be one of
12 * "adi,adis16495-1"
13 * "adi,adis16495-2"
14 * "adi,adis16495-3"
15 * "adi,adis16497-1"
16 * "adi,adis16497-2"
17 * "adi,adis16497-3"
18 - reg: SPI chip select number for the device
19 - spi-max-frequency: Max SPI frequency to use
20 see: Documentation/devicetree/bindings/spi/spi-bus.txt
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/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/tests/mali_kutf_clk_rate_trace/
H A Dmali_kutf_clk_rate_trace_test.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
8 * Foundation, and any use by you of this program is subject to the terms
18 * http://www.gnu.org/licenses/gpl-2.0.html.
30 * enum kbasep_clk_rate_trace_req - request command to the clock rate trace
35 * @PORTAL_CMD_GET_CLK_RATE_MGR: Request the clock trace manager internal
37 * the prevailing clock rates and the GPU idle
39 * @PORTAL_CMD_GET_CLK_RATE_TRACE: Request the clock trace portal to return its
41 * the last trace recorded clock rates and the
43 * @PORTAL_CMD_GET_TRACE_SNAPSHOT: Request the clock trace portal to return its
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/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-of-at91.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/mmc/slot-gpio.h>
24 #include "sdhci-pltfm.h"
36 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
57 mc1r = readb(host->ioaddr + SDMMC_MC1R); in sdhci_at91_set_force_card_detect()
59 writeb(mc1r, host->ioaddr + SDMMC_MC1R); in sdhci_at91_set_force_card_detect()
62 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) in sdhci_at91_set_clock() argument
66 host->mmc->actual_clock = 0; in sdhci_at91_set_clock()
69 * There is no requirement to disable the internal clock before in sdhci_at91_set_clock()
70 * changing the SD clock configuration. Moreover, disabling the in sdhci_at91_set_clock()
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/OK3568_Linux_fs/kernel/drivers/staging/comedi/
H A Dcomedi.h1 /* SPDX-License-Identifier: LGPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
24 * don't want this to be much more than you actually use.
32 * NOTE: 'comedi_config --init-data' is deprecated
40 /* length of nth chunk of firmware data -*/
78 /* counters -- these are arbitrary values */
120 /* try to use a real-time interrupt while performing command */
123 /* wake up on end-of-scan events */
166 #define TRIG_INT 0x00000080 /* trigger on comedi-internal signal N */
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/OK3568_Linux_fs/kernel/sound/pci/echoaudio/
H A Dlayla24_dsp.c3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA.
25 Translation from C++ and adaptation for use in ALSA-Driver
32 static int set_input_clock(struct echoaudio *chip, u16 clock);
44 return -ENODEV; in init_hw()
47 dev_err(chip->card->dev, in init_hw()
48 "init_hw - could not initialize DSP comm page\n"); in init_hw()
52 chip->device_id = device_id; in init_hw()
53 chip->subdevice_id = subdevice_id; in init_hw()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@st.com>
11 - Olivier Moysan <olivier.moysan@st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
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/OK3568_Linux_fs/kernel/include/uapi/misc/
H A Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2020 HabanaLabs, Ltd.
15 * Defines that are asic-specific but constitutes as ABI between kernel driver
26 * The external queues (PCI DMA channels) MUST be before the internal queues
27 * and each group (PCI DMA channels and internal) must be contiguous inside
39 GOYA_QUEUE_ID_MME = 6, /* Internal queues start here */
54 * Except one CPU queue, all the rest are internal queues.
67 GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */
68 GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */
69 GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */
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/OK3568_Linux_fs/kernel/Documentation/sound/soc/
H A Ddapm.rst9 Linux devices to use the minimum amount of power within the audio
11 such, can easily co-exist with the other PM systems.
20 audio subsystem, this includes internal codec power blocks and machine
53 internal codec components). All audio components that effect power are called
60 Audio DAPM widgets fall into a number of types:-
87 Power or clock supply widget used by other widgets.
90 Clock
91 External clock that supplies clock to audio components.
111 DSP internal scheduler that schedules component/pipeline processing
127 (Widgets are defined in include/sound/soc-dapm.h)
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/OK3568_Linux_fs/kernel/include/soc/at91/
H A Datmel_tcb.h17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
19 * Depending on the SOC, each timer may have its own clock and IRQ, or those
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
24 * or triggering. Those pins need to be set up for use with the TC block,
30 * timers. Then they use clk_get() and platform_get_irq() to get clock and
37 * struct atmel_tcb_config - SoC data for a Timer/Counter Block
39 * @has_gclk: boolean indicating if a timer counter has a generic clock
50 * struct atmel_tc - information about a Timer/Counter Block
56 * @clk: internal clock source for each of the three channels
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h4 * SPDX-License-Identifier: GPL-2.0+
7 /* Tegra clock control functions */
12 /* Set of oscillator frequencies supported in the internal API. */
26 * Note that no Tegra clock register actually uses all of bits 31:28 as
30 * register. As such, the U-Boot clock driver is currently a bit lazy, and
40 #include <asm/arch/clock-tables.h>
44 /* return the current oscillator clock frequency */
53 * @param id clock id
68 * @param clkid clock id
72 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dphy-mtk-xsphy.txt1 MediaTek XS-PHY binding
2 --------------------------
4 The XS-PHY controller supports physical layer functionality for USB3.1
8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
9 soc-model is the name of SoC, such as mt3611 etc;
12 - "mediatek,mt3611-xsphy"
14 - #address-cells, #size-cells : should use the same values as the root node
15 - ranges: must be present
18 - reg : offset and length of register shared by multiple U3 ports,
20 shouldn't use the property.
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/inc/
H A Dsmu11_driver_if_navi10.h7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
50 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
51 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
52 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
53 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
54 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
55 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
56 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
57 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
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