1*4882a593SmuzhiyunMediaTek XS-PHY binding 2*4882a593Smuzhiyun-------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe XS-PHY controller supports physical layer functionality for USB3.1 5*4882a593SmuzhiyunGEN2 controller on MediaTek SoCs. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties (controller (parent) node): 8*4882a593Smuzhiyun - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy", 9*4882a593Smuzhiyun soc-model is the name of SoC, such as mt3611 etc; 10*4882a593Smuzhiyun when using "mediatek,xsphy" compatible string, you need SoC specific 11*4882a593Smuzhiyun ones in addition, one of: 12*4882a593Smuzhiyun - "mediatek,mt3611-xsphy" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun - #address-cells, #size-cells : should use the same values as the root node 15*4882a593Smuzhiyun - ranges: must be present 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties (controller (parent) node): 18*4882a593Smuzhiyun - reg : offset and length of register shared by multiple U3 ports, 19*4882a593Smuzhiyun exclude port's private register, if only U2 ports provided, 20*4882a593Smuzhiyun shouldn't use the property. 21*4882a593Smuzhiyun - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate 22*4882a593Smuzhiyun calibrate 23*4882a593Smuzhiyun - mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on 24*4882a593Smuzhiyun SoC process 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunRequired nodes : a sub-node is required for each port the controller 27*4882a593Smuzhiyun provides. Address range information including the usual 28*4882a593Smuzhiyun 'reg' property is used inside these nodes to describe 29*4882a593Smuzhiyun the controller's topology. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunRequired properties (port (child) node): 32*4882a593Smuzhiyun- reg : address and length of the register set for the port. 33*4882a593Smuzhiyun- clocks : a list of phandle + clock-specifier pairs, one for each 34*4882a593Smuzhiyun entry in clock-names 35*4882a593Smuzhiyun- clock-names : must contain 36*4882a593Smuzhiyun "ref": 48M reference clock for HighSpeed analog phy; and 26M 37*4882a593Smuzhiyun reference clock for SuperSpeedPlus analog phy, sometimes is 38*4882a593Smuzhiyun 24M, 25M or 27M, depended on platform. 39*4882a593Smuzhiyun- #phy-cells : should be 1 40*4882a593Smuzhiyun cell after port phandle is phy type from: 41*4882a593Smuzhiyun - PHY_TYPE_USB2 42*4882a593Smuzhiyun - PHY_TYPE_USB3 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunThe following optional properties are only for debug or HQA test 45*4882a593SmuzhiyunOptional properties (PHY_TYPE_USB2 port (child) node): 46*4882a593Smuzhiyun- mediatek,eye-src : u32, the value of slew rate calibrate 47*4882a593Smuzhiyun- mediatek,eye-vrt : u32, the selection of VRT reference voltage 48*4882a593Smuzhiyun- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage 49*4882a593Smuzhiyun- mediatek,efuse-intr : u32, the selection of Internal Resistor 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunOptional properties (PHY_TYPE_USB3 port (child) node): 52*4882a593Smuzhiyun- mediatek,efuse-intr : u32, the selection of Internal Resistor 53*4882a593Smuzhiyun- mediatek,efuse-tx-imp : u32, the selection of TX Impedance 54*4882a593Smuzhiyun- mediatek,efuse-rx-imp : u32, the selection of RX Impedance 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunBanks layout of xsphy 57*4882a593Smuzhiyun------------------------------------------------------------- 58*4882a593Smuzhiyunport offset bank 59*4882a593Smuzhiyunu2 port0 0x0000 MISC 60*4882a593Smuzhiyun 0x0100 FMREG 61*4882a593Smuzhiyun 0x0300 U2PHY_COM 62*4882a593Smuzhiyunu2 port1 0x1000 MISC 63*4882a593Smuzhiyun 0x1100 FMREG 64*4882a593Smuzhiyun 0x1300 U2PHY_COM 65*4882a593Smuzhiyunu2 port2 0x2000 MISC 66*4882a593Smuzhiyun ... 67*4882a593Smuzhiyunu31 common 0x3000 DIG_GLB 68*4882a593Smuzhiyun 0x3100 PHYA_GLB 69*4882a593Smuzhiyunu31 port0 0x3400 DIG_LN_TOP 70*4882a593Smuzhiyun 0x3500 DIG_LN_TX0 71*4882a593Smuzhiyun 0x3600 DIG_LN_RX0 72*4882a593Smuzhiyun 0x3700 DIG_LN_DAIF 73*4882a593Smuzhiyun 0x3800 PHYA_LN 74*4882a593Smuzhiyunu31 port1 0x3a00 DIG_LN_TOP 75*4882a593Smuzhiyun 0x3b00 DIG_LN_TX0 76*4882a593Smuzhiyun 0x3c00 DIG_LN_RX0 77*4882a593Smuzhiyun 0x3d00 DIG_LN_DAIF 78*4882a593Smuzhiyun 0x3e00 PHYA_LN 79*4882a593Smuzhiyun ... 80*4882a593Smuzhiyun 81*4882a593SmuzhiyunDIG_GLB & PHYA_GLB are shared by U31 ports. 82*4882a593Smuzhiyun 83*4882a593SmuzhiyunExample: 84*4882a593Smuzhiyun 85*4882a593Smuzhiyunu3phy: usb-phy@11c40000 { 86*4882a593Smuzhiyun compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy"; 87*4882a593Smuzhiyun reg = <0 0x11c43000 0 0x0200>; 88*4882a593Smuzhiyun mediatek,src-ref-clk-mhz = <26>; 89*4882a593Smuzhiyun mediatek,src-coef = <17>; 90*4882a593Smuzhiyun #address-cells = <2>; 91*4882a593Smuzhiyun #size-cells = <2>; 92*4882a593Smuzhiyun ranges; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun u2port0: usb-phy@11c40000 { 95*4882a593Smuzhiyun reg = <0 0x11c40000 0 0x0400>; 96*4882a593Smuzhiyun clocks = <&clk48m>; 97*4882a593Smuzhiyun clock-names = "ref"; 98*4882a593Smuzhiyun mediatek,eye-src = <4>; 99*4882a593Smuzhiyun #phy-cells = <1>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun u3port0: usb-phy@11c43000 { 103*4882a593Smuzhiyun reg = <0 0x11c43400 0 0x0500>; 104*4882a593Smuzhiyun clocks = <&clk26m>; 105*4882a593Smuzhiyun clock-names = "ref"; 106*4882a593Smuzhiyun mediatek,efuse-intr = <28>; 107*4882a593Smuzhiyun #phy-cells = <1>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun}; 110