1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2013 Emilio López
4*4882a593Smuzhiyun * Emilio López <emilio@elopez.com.ar>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright 2013 Chen-Yu Tsai
7*4882a593Smuzhiyun * Chen-Yu Tsai <wens@csie.org>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk-provider.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/of_address.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static DEFINE_SPINLOCK(gmac_lock);
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /**
19*4882a593Smuzhiyun * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * This clock looks something like this
22*4882a593Smuzhiyun * ________________________
23*4882a593Smuzhiyun * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24*4882a593Smuzhiyun * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25*4882a593Smuzhiyun * Ext. 125MHz RGMII TX clk >--|__divider__/ |
26*4882a593Smuzhiyun * |________________________|
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * The external 125 MHz reference is optional, i.e. GMAC can use its
29*4882a593Smuzhiyun * internal TX clock just fine. The A31 GMAC clock module does not have
30*4882a593Smuzhiyun * the divider controls for the external reference.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
33*4882a593Smuzhiyun * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
34*4882a593Smuzhiyun * select the appropriate source and gate/ungate the output to the PHY.
35*4882a593Smuzhiyun *
36*4882a593Smuzhiyun * Only the GMAC should use this clock. Altering the clock so that it doesn't
37*4882a593Smuzhiyun * match the GMAC's operation parameters will result in the GMAC not being
38*4882a593Smuzhiyun * able to send traffic out. The GMAC driver should set the clock rate and
39*4882a593Smuzhiyun * enable/disable this clock to configure the required state. The clock
40*4882a593Smuzhiyun * driver then responds by auto-reparenting the clock.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define SUN7I_A20_GMAC_GPIT 2
44*4882a593Smuzhiyun #define SUN7I_A20_GMAC_MASK 0x3
45*4882a593Smuzhiyun #define SUN7I_A20_GMAC_PARENTS 2
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static u32 sun7i_a20_gmac_mux_table[SUN7I_A20_GMAC_PARENTS] = {
48*4882a593Smuzhiyun 0x00, /* Select mii_phy_tx_clk */
49*4882a593Smuzhiyun 0x02, /* Select gmac_int_tx_clk */
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
sun7i_a20_gmac_clk_setup(struct device_node * node)52*4882a593Smuzhiyun static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct clk *clk;
55*4882a593Smuzhiyun struct clk_mux *mux;
56*4882a593Smuzhiyun struct clk_gate *gate;
57*4882a593Smuzhiyun const char *clk_name = node->name;
58*4882a593Smuzhiyun const char *parents[SUN7I_A20_GMAC_PARENTS];
59*4882a593Smuzhiyun void __iomem *reg;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun if (of_property_read_string(node, "clock-output-names", &clk_name))
62*4882a593Smuzhiyun return;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* allocate mux and gate clock structs */
65*4882a593Smuzhiyun mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
66*4882a593Smuzhiyun if (!mux)
67*4882a593Smuzhiyun return;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
70*4882a593Smuzhiyun if (!gate)
71*4882a593Smuzhiyun goto free_mux;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* gmac clock requires exactly 2 parents */
74*4882a593Smuzhiyun if (of_clk_parent_fill(node, parents, 2) != 2)
75*4882a593Smuzhiyun goto free_gate;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun reg = of_iomap(node, 0);
78*4882a593Smuzhiyun if (!reg)
79*4882a593Smuzhiyun goto free_gate;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* set up gate and fixed rate properties */
82*4882a593Smuzhiyun gate->reg = reg;
83*4882a593Smuzhiyun gate->bit_idx = SUN7I_A20_GMAC_GPIT;
84*4882a593Smuzhiyun gate->lock = &gmac_lock;
85*4882a593Smuzhiyun mux->reg = reg;
86*4882a593Smuzhiyun mux->mask = SUN7I_A20_GMAC_MASK;
87*4882a593Smuzhiyun mux->table = sun7i_a20_gmac_mux_table;
88*4882a593Smuzhiyun mux->lock = &gmac_lock;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun clk = clk_register_composite(NULL, clk_name,
91*4882a593Smuzhiyun parents, SUN7I_A20_GMAC_PARENTS,
92*4882a593Smuzhiyun &mux->hw, &clk_mux_ops,
93*4882a593Smuzhiyun NULL, NULL,
94*4882a593Smuzhiyun &gate->hw, &clk_gate_ops,
95*4882a593Smuzhiyun 0);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (IS_ERR(clk))
98*4882a593Smuzhiyun goto iounmap_reg;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun of_clk_add_provider(node, of_clk_src_simple_get, clk);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun iounmap_reg:
105*4882a593Smuzhiyun iounmap(reg);
106*4882a593Smuzhiyun free_gate:
107*4882a593Smuzhiyun kfree(gate);
108*4882a593Smuzhiyun free_mux:
109*4882a593Smuzhiyun kfree(mux);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
112*4882a593Smuzhiyun sun7i_a20_gmac_clk_setup);
113