| /OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 11 ---------
12 The LS1043A integrated multicore processor combines four ARM Cortex-A53
18 - Four 64-bit ARM Cortex-A53 CPUs
19 - 1 MB unified L2 Cache
20 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
22 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
24 - Packet parsing, classification, and distribution (FMan)
25 - Queue management for scheduling, packet sequencing, and congestion
27 - Hardware buffer management for buffer allocation and de-allocation (BMan)
28 - Cryptography acceleration (SEC)
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| /OK3568_Linux_fs/kernel/Documentation/admin-guide/ |
| H A D | cgroup-v2.rst | 9 conventions of cgroup v2. It describes all userland-visible aspects
12 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
17 1-1. Terminology
18 1-2. What is cgroup?
20 2-1. Mounting
21 2-2. Organizing Processes and Threads
22 2-2-1. Processes
23 2-2-2. Threads
24 2-3. [Un]populated Notification
25 2-4. Controlling Controllers
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| /OK3568_Linux_fs/kernel/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
16 * Memory devices
18 The individual DRAM chips on a memory stick. These devices commonly
20 provides the number of bits that the memory controller expects:
23 * Memory Stick
25 A printed circuit board that aggregates multiple memory devices in
28 called DIMM (Dual Inline Memory Module).
30 * Memory Socket
32 A physical connector on the motherboard that accepts a single memory
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| /OK3568_Linux_fs/kernel/drivers/edac/ |
| H A D | Kconfig | 16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
59 Not all machines support hardware-driven error report. Some of those
60 provide a BIOS-driven error report mechanism via ACPI, using the
64 When this option is enabled, it will disable the hardware-driven
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| /OK3568_Linux_fs/kernel/include/linux/mux/ |
| H A D | driver.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mux/driver.h - definitions for the multiplexer driver interface
13 #include <dt-bindings/mux/mux.h>
21 * struct mux_control_ops - Mux controller operations for a mux chip.
29 * struct mux_control - Represents a mux controller.
32 * @cached_state: The current mux controller state, or -1 if none.
53 * struct mux_chip - Represents a chip holding mux controllers.
54 * @controllers: Number of mux controllers handled by the chip.
55 * @mux: Array of mux controllers that are handled.
61 unsigned int controllers; member
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| /OK3568_Linux_fs/kernel/drivers/mmc/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
64 and Toshiba(R). Most controllers found in laptops are of this type.
76 need to overwrite SDHCI IO memory accessors.
85 implements a hardware byte swapper using a 32-bit datum.
100 Most controllers found today are PCI devices.
114 disabled, it will steal the MMC cards away - rendering them
121 tristate "SDHCI support for ACPI enumerated SDHCI controllers"
125 This selects support for ACPI enumerated SDHCI controllers,
145 tristate "SDHCI OF support for the Arasan SDHCI controllers"
192 tristate "SDHCI OF support for the Nintendo Wii SDHCI controllers"
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | renesas,dbsc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Renesas DDR Bus Controllers
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 Renesas SoCs contain one or more memory controllers. These memory
14 controllers differ from one SoC variant to another, and are called by
21 - renesas,dbsc-r8a73a4 # R-Mobile APE6
22 - renesas,dbsc3-r8a7740 # R-Mobile A1
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mips/brcm/ |
| H A D | soc.txt | 5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
12 The experimental -viper variants are for running Linux on the 3384's
16 ----------------
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
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| /OK3568_Linux_fs/u-boot/board/freescale/t1040qds/ |
| H A D | README | 2 --------
7 ------------------
8 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
9 processor cores with high-performance data path acceleration architecture
14 - Four e5500 cores, each with a private 256 KB L2 cache
15 - 256 KB shared L3 CoreNet platform cache (CPC)
16 - Interconnect CoreNet platform
17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
19 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
21 - Packet parsing, classification, and distribution
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/ |
| H A D | gpmc-eth.txt | 3 Besides being used to interface with external memory devices, the
4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
5 such as ethernet controllers to processors using the TI GPMC as a data bus.
7 Ethernet controllers connected to TI GPMC are represented as child nodes of
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/t208xqds/ |
| H A D | README | 1 The T2080QDS is a high-performance computing evaluation, development and
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
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| /OK3568_Linux_fs/kernel/drivers/scsi/aic7xxx/ |
| H A D | aic7xxx_osm_pci.c | 2 * Linux driver attachment glue for PCI based controllers.
4 * Copyright (c) 2000-2001 Adaptec Inc.
18 * 3. Neither the names of the above-listed copyright holders nor the names
50 /* aic7850 based controllers */
52 /* aic7860 based controllers */
58 /* aic7870 based controllers */
65 /* aic7880 based controllers */
75 /* aic7890 based controllers */
83 /* aic7890 based controllers */
91 /* aic7892 based controllers */
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| /OK3568_Linux_fs/u-boot/drivers/core/ |
| H A D | Kconfig | 7 support, including scanning of platform data on start-up. If
45 This will cause dm_warn() to be compiled out - it will do nothing
64 it causes unplugged devices to linger around in the dm-tree, and it
65 causes USB host controllers to not be stopped when booting the OS.
102 direct memory access.
112 direct memory access.
122 direct memory access.
125 bool "Support system controllers"
128 Many SoCs have a number of system controllers which are dealt with
134 bool "Support system controllers in SPL"
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| /OK3568_Linux_fs/u-boot/board/freescale/ls1012ardb/ |
| H A D | README | 2 --------
3 QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
6 optimized to support the high-bandwidth DDR3L memory and
7 a full complement of high-speed SerDes ports.
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
15 -----------------------
16 - SERDES Connections, 4 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/bcm/ |
| H A D | brcm,brcmstb.txt | 2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
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| /OK3568_Linux_fs/u-boot/drivers/mmc/ |
| H A D | Kconfig | 21 bool "Enable MMC controllers using Driver Model"
25 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
26 and non-removable (e.g. eMMC chip) devices are supported. These
27 appear as block devices in U-Boot and can support filesystems such
31 bool "Enable MMC controllers using Driver Model in SPL"
36 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
37 and non-removable (e.g. eMMC chip) devices are supported. These
38 appear as block devices in U-Boot and can support filesystems such
49 you are reading this help text, you most likely have no idea :-)
64 bool "Support eMMC replay protected memory block (RPMB)"
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/ |
| H A D | aspeed-smc.txt | 1 * Aspeed Firmware Memory controller
2 * Aspeed SPI Flash Memory Controller
4 The Firmware Memory Controller in the Aspeed AST2500 SoC supports
8 The two SPI flash memory controllers in the AST2500 each support two
12 - compatible : Should be one of
13 "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15 "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
18 - reg : the first contains the control register location and length,
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/ls1021atwr/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/core-api/ |
| H A D | debugging-via-ohci1394.rst | 2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
6 ------------
8 Basically all FireWire controllers which are in use today are compliant
9 to the OHCI-1394 specification which defines the controller to be a PCI
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
15 ask the OHCI-1394 controller to perform read and write requests on
16 physical system memory and, for read requests, send the result of
17 the physical memory read back to the requester.
19 With that, it is possible to debug issues by reading interesting memory
22 Retrieving a full system memory dump is also possible over the FireWire,
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/ls1021aqds/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
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| /OK3568_Linux_fs/kernel/drivers/scsi/megaraid/ |
| H A D | megaraid_mbox.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (c) 2003-2004 LSI Logic Corporation.
94 #define MBOX_MAX_SG_SIZE 32 // maximum scatter-gather list size
102 #define MBOX_SYNC_DELAY_200 200 // 200 micro-seconds
112 * mbox_ccb_t - command control block specific to mailbox based controllers
117 * @sgl64 : 64-bit scatter-gather list
118 * @sgl32 : 32-bit scatter-gather list
119 * @sgl_dma_h : dma handle for the scatter-gather list
126 * command control block specific to the mailbox based controllers
145 * mraid_device_t - adapter soft state structure for mailbox controllers
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/ |
| H A D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/t102xrdb/ |
| H A D | README | 2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/t208xrdb/ |
| H A D | README | 1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
[all …]
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| /OK3568_Linux_fs/u-boot/include/ |
| H A D | spi-mem.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
61 * enum spi_mem_data_dir - describes the direction of a SPI memory data
63 * @SPI_MEM_DATA_IN: data coming from the SPI memory
64 * @SPI_MEM_DATA_OUT: data sent the SPI memory
72 * struct spi_mem_op - describes a SPI memory operation
111 /* buf.{in,out} must be DMA-able. */
129 * struct spi_mem - describes a SPI memory device
133 * Extra information that describe the SPI memory device and may be needed by
137 * mem devices through a io-mapped region.
145 * struct spi_mem_set_drvdata() - attach driver private data to a SPI mem
[all …]
|