1*4882a593SmuzhiyunOverview 2*4882a593Smuzhiyun-------- 3*4882a593SmuzhiyunThe LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunLS1021A SoC Overview 6*4882a593Smuzhiyun------------------ 7*4882a593SmuzhiyunThe QorIQ LS1 family, which includes the LS1021A communications processor, 8*4882a593Smuzhiyunis built on Layerscape architecture, the industry's first software-aware, 9*4882a593Smuzhiyuncore-agnostic networking architecture to offer unprecedented efficiency 10*4882a593Smuzhiyunand scale. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunA member of the value-performance tier, the QorIQ LS1021A processor provides 13*4882a593Smuzhiyunextensive integration and power efficiency for fanless, small form factor 14*4882a593Smuzhiyunenterprise networking applications. Incorporating dual ARM Cortex-A7 cores 15*4882a593Smuzhiyunrunning up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark 16*4882a593Smuzhiyunperformance of over 6,000, as well as virtualization support, advanced 17*4882a593Smuzhiyunsecurity features and the broadest array of high-speed interconnects and 18*4882a593Smuzhiyunoptimized peripheral features ever offered in a sub-3 W processor. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunThe QorIQ LS1021A processor features an integrated LCD controller, 21*4882a593SmuzhiyunCAN controller for implementing industrial protocols, DDR3L/4 running 22*4882a593Smuzhiyunup to 1600 MHz, integrated security engine and QUICC Engine, and ECC 23*4882a593Smuzhiyunprotection on both L1 and L2 caches. The LS1021A processor is pin- and 24*4882a593Smuzhiyunsoftware-compatible with the QorIQ LS1020A and LS1022A processors. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunThe LS1021A SoC includes the following function and features: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture 29*4882a593Smuzhiyun - Dual high-preformance ARM Cortex-A7 cores, each core includes: 30*4882a593Smuzhiyun - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) 31*4882a593Smuzhiyun - 512 Kbyte shared coherent L2 Cache (with ECC protection) 32*4882a593Smuzhiyun - NEON Co-processor (per core) 33*4882a593Smuzhiyun - 40-bit physical addressing 34*4882a593Smuzhiyun - Vector floating-point support 35*4882a593Smuzhiyun - ARM Core-Link CCI-400 Cache Coherent Interconnect 36*4882a593Smuzhiyun - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration 37*4882a593Smuzhiyun supporting speeds up to 1600Mtps 38*4882a593Smuzhiyun - ECC and interleaving support 39*4882a593Smuzhiyun - VeTSEC Ethernet complex 40*4882a593Smuzhiyun - Up to 3x virtualized 10/100/1000 Ethernet controllers 41*4882a593Smuzhiyun - MII, RMII, RGMII, and SGMII support 42*4882a593Smuzhiyun - QoS, lossless flow control, and IEEE 1588 support 43*4882a593Smuzhiyun - 4-lane 6GHz SerDes 44*4882a593Smuzhiyun - High speed interconnect (4 SerDes lanes with are muxed for these protocol) 45*4882a593Smuzhiyun - Two PCI Express Gen2 controllers running at up to 5 GHz 46*4882a593Smuzhiyun - One Serial ATA 3.0 supporting 6 GT/s operation 47*4882a593Smuzhiyun - Two SGMII interfaces supporting 1000 Mbps 48*4882a593Smuzhiyun - Additional peripheral interfaces 49*4882a593Smuzhiyun - One high-speed USB 3.0 controller with integrated PHY and one high-speed 50*4882a593Smuzhiyun USB 2.00 controller with ULPI 51*4882a593Smuzhiyun - Integrated flash controller (IFC) with 16-bit interface 52*4882a593Smuzhiyun - Quad SPI NOR Flash 53*4882a593Smuzhiyun - One enhanced Secure digital host controller 54*4882a593Smuzhiyun - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) 55*4882a593Smuzhiyun - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power 56*4882a593Smuzhiyun UARTs 57*4882a593Smuzhiyun - Three I2C controllers 58*4882a593Smuzhiyun - Eight FlexTimers four supporting PWM and four FlexCAN ports 59*4882a593Smuzhiyun - Four GPIO controllers supporting up to 109 general purpose I/O signals 60*4882a593Smuzhiyun - Integrated advanced audio block: 61*4882a593Smuzhiyun - Four synchronous audio interfaces (SAI) 62*4882a593Smuzhiyun - Sony/Philips Digital Interconnect Format (SPDIF) 63*4882a593Smuzhiyun - Asynchronous Sample Rate Converter (ASRC) 64*4882a593Smuzhiyun - Hardware based crypto offload engine 65*4882a593Smuzhiyun - IPSec forwarding at up to 1Gbps 66*4882a593Smuzhiyun - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported 67*4882a593Smuzhiyun - Public key hardware accelerator 68*4882a593Smuzhiyun - True Random Number Generator (NIST Certified) 69*4882a593Smuzhiyun - Advanced Encryption Standard Accelerators (AESA) 70*4882a593Smuzhiyun - Data Encryption Standard Accelerators 71*4882a593Smuzhiyun - QUICC Engine ULite block 72*4882a593Smuzhiyun - Two universal communication controllers (TDM and HDLC) supporting 64 73*4882a593Smuzhiyun multichannels, each running at 64 Kbps 74*4882a593Smuzhiyun - Support for 256 channels of HDLC 75*4882a593Smuzhiyun - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported 76*4882a593Smuzhiyun 77*4882a593SmuzhiyunLS1021AQDS board Overview 78*4882a593Smuzhiyun------------------------- 79*4882a593Smuzhiyun - DDR Controller 80*4882a593Smuzhiyun - Supports rates of up to 1600 MHz data-rate 81*4882a593Smuzhiyun - Supports one DDR3LP UDIMM, of single-, dual- types. 82*4882a593Smuzhiyun - IFC/Local Bus 83*4882a593Smuzhiyun - NAND flash: 512M 8-bit NAND flash 84*4882a593Smuzhiyun - NOR: 128MB 16-bit NOR Flash 85*4882a593Smuzhiyun - Ethernet 86*4882a593Smuzhiyun - Three on-board RGMII 10/100/1G ethernet ports. 87*4882a593Smuzhiyun - FPGA 88*4882a593Smuzhiyun - Clocks 89*4882a593Smuzhiyun - System and DDR clock (SYSCLK, DDRCLK) 90*4882a593Smuzhiyun - SERDES clocks 91*4882a593Smuzhiyun - Power Supplies 92*4882a593Smuzhiyun - SDHC 93*4882a593Smuzhiyun - SDHC/SDXC connector 94*4882a593Smuzhiyun - Other IO 95*4882a593Smuzhiyun - Two Serial ports 96*4882a593Smuzhiyun - Three I2C ports 97*4882a593Smuzhiyun 98*4882a593SmuzhiyunMemory map 99*4882a593Smuzhiyun----------- 100*4882a593SmuzhiyunThe addresses in brackets are physical addresses. 101*4882a593Smuzhiyun 102*4882a593SmuzhiyunStart Address End Address Description Size 103*4882a593Smuzhiyun0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB 104*4882a593Smuzhiyun0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB 105*4882a593Smuzhiyun0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB 106*4882a593Smuzhiyun0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB 107*4882a593Smuzhiyun0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB 108*4882a593Smuzhiyun0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB 109*4882a593Smuzhiyun0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB 110*4882a593Smuzhiyun0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB 111*4882a593Smuzhiyun0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB 112*4882a593Smuzhiyun0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB 113*4882a593Smuzhiyun 114*4882a593SmuzhiyunLS1021a rev1.0 Soc specific Options/Settings 115*4882a593Smuzhiyun-------------------------------------------- 116*4882a593SmuzhiyunIf the LS1021a Soc is rev1.0, you need modify the configure file. 117*4882a593SmuzhiyunAdd the following define in include/configs/ls1021aqds.h: 118*4882a593Smuzhiyun#define CONFIG_SKIP_LOWLEVEL_INIT 119