1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Linux MegaRAID device driver 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (c) 2003-2004 LSI Logic Corporation. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * FILE : megaraid_mbox.h 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _MEGARAID_H_ 12*4882a593Smuzhiyun #define _MEGARAID_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include "mega_common.h" 16*4882a593Smuzhiyun #include "mbox_defs.h" 17*4882a593Smuzhiyun #include "megaraid_ioctl.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define MEGARAID_VERSION "2.20.5.1" 21*4882a593Smuzhiyun #define MEGARAID_EXT_VERSION "(Release Date: Thu Nov 16 15:32:35 EST 2006)" 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * Define some PCI values here until they are put in the kernel 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define PCI_DEVICE_ID_PERC4_DI_DISCOVERY 0x000E 28*4882a593Smuzhiyun #define PCI_SUBSYS_ID_PERC4_DI_DISCOVERY 0x0123 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define PCI_DEVICE_ID_PERC4_SC 0x1960 31*4882a593Smuzhiyun #define PCI_SUBSYS_ID_PERC4_SC 0x0520 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define PCI_DEVICE_ID_PERC4_DC 0x1960 34*4882a593Smuzhiyun #define PCI_SUBSYS_ID_PERC4_DC 0x0518 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define PCI_DEVICE_ID_VERDE 0x0407 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define PCI_DEVICE_ID_PERC4_DI_EVERGLADES 0x000F 39*4882a593Smuzhiyun #define PCI_SUBSYS_ID_PERC4_DI_EVERGLADES 0x014A 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define PCI_DEVICE_ID_PERC4E_SI_BIGBEND 0x0013 42*4882a593Smuzhiyun #define PCI_SUBSYS_ID_PERC4E_SI_BIGBEND 0x016c 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define PCI_DEVICE_ID_PERC4E_DI_KOBUK 0x0013 45*4882a593Smuzhiyun #define PCI_SUBSYS_ID_PERC4E_DI_KOBUK 0x016d 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define PCI_DEVICE_ID_PERC4E_DI_CORVETTE 0x0013 48*4882a593Smuzhiyun #define PCI_SUBSYS_ID_PERC4E_DI_CORVETTE 0x016e 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define PCI_DEVICE_ID_PERC4E_DI_EXPEDITION 0x0013 51*4882a593Smuzhiyun #define PCI_SUBSYS_ID_PERC4E_DI_EXPEDITION 0x016f 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define PCI_DEVICE_ID_PERC4E_DI_GUADALUPE 0x0013 54*4882a593Smuzhiyun #define PCI_SUBSYS_ID_PERC4E_DI_GUADALUPE 0x0170 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define PCI_DEVICE_ID_DOBSON 0x0408 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define PCI_DEVICE_ID_MEGARAID_SCSI_320_0 0x1960 59*4882a593Smuzhiyun #define PCI_SUBSYS_ID_MEGARAID_SCSI_320_0 0xA520 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define PCI_DEVICE_ID_MEGARAID_SCSI_320_1 0x1960 62*4882a593Smuzhiyun #define PCI_SUBSYS_ID_MEGARAID_SCSI_320_1 0x0520 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define PCI_DEVICE_ID_MEGARAID_SCSI_320_2 0x1960 65*4882a593Smuzhiyun #define PCI_SUBSYS_ID_MEGARAID_SCSI_320_2 0x0518 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define PCI_DEVICE_ID_MEGARAID_I4_133_RAID 0x1960 68*4882a593Smuzhiyun #define PCI_SUBSYS_ID_MEGARAID_I4_133_RAID 0x0522 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define PCI_DEVICE_ID_MEGARAID_SATA_150_4 0x1960 71*4882a593Smuzhiyun #define PCI_SUBSYS_ID_MEGARAID_SATA_150_4 0x4523 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define PCI_DEVICE_ID_MEGARAID_SATA_150_6 0x1960 74*4882a593Smuzhiyun #define PCI_SUBSYS_ID_MEGARAID_SATA_150_6 0x0523 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define PCI_DEVICE_ID_LINDSAY 0x0409 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_RAID_SRCS16 0x1960 79*4882a593Smuzhiyun #define PCI_SUBSYS_ID_INTEL_RAID_SRCS16 0x0523 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK 0x1960 82*4882a593Smuzhiyun #define PCI_SUBSYS_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK 0x0520 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define PCI_SUBSYS_ID_PERC3_QC 0x0471 85*4882a593Smuzhiyun #define PCI_SUBSYS_ID_PERC3_DC 0x0493 86*4882a593Smuzhiyun #define PCI_SUBSYS_ID_PERC3_SC 0x0475 87*4882a593Smuzhiyun #define PCI_SUBSYS_ID_CERC_ATA100_4CH 0x0511 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define MBOX_MAX_SCSI_CMDS 128 // number of cmds reserved for kernel 91*4882a593Smuzhiyun #define MBOX_MAX_USER_CMDS 32 // number of cmds for applications 92*4882a593Smuzhiyun #define MBOX_DEF_CMD_PER_LUN 64 // default commands per lun 93*4882a593Smuzhiyun #define MBOX_DEFAULT_SG_SIZE 26 // default sg size supported by all fw 94*4882a593Smuzhiyun #define MBOX_MAX_SG_SIZE 32 // maximum scatter-gather list size 95*4882a593Smuzhiyun #define MBOX_MAX_SECTORS 128 // maximum sectors per IO 96*4882a593Smuzhiyun #define MBOX_TIMEOUT 30 // timeout value for internal cmds 97*4882a593Smuzhiyun #define MBOX_BUSY_WAIT 10 // max usec to wait for busy mailbox 98*4882a593Smuzhiyun #define MBOX_RESET_WAIT 180 // wait these many seconds in reset 99*4882a593Smuzhiyun #define MBOX_RESET_EXT_WAIT 120 // extended wait reset 100*4882a593Smuzhiyun #define MBOX_SYNC_WAIT_CNT 0xFFFF // wait loop index for synchronous mode 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define MBOX_SYNC_DELAY_200 200 // 200 micro-seconds 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* 105*4882a593Smuzhiyun * maximum transfer that can happen through the firmware commands issued 106*4882a593Smuzhiyun * internnaly from the driver. 107*4882a593Smuzhiyun */ 108*4882a593Smuzhiyun #define MBOX_IBUF_SIZE 4096 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /** 112*4882a593Smuzhiyun * mbox_ccb_t - command control block specific to mailbox based controllers 113*4882a593Smuzhiyun * @raw_mbox : raw mailbox pointer 114*4882a593Smuzhiyun * @mbox : mailbox 115*4882a593Smuzhiyun * @mbox64 : extended mailbox 116*4882a593Smuzhiyun * @mbox_dma_h : mailbox dma address 117*4882a593Smuzhiyun * @sgl64 : 64-bit scatter-gather list 118*4882a593Smuzhiyun * @sgl32 : 32-bit scatter-gather list 119*4882a593Smuzhiyun * @sgl_dma_h : dma handle for the scatter-gather list 120*4882a593Smuzhiyun * @pthru : passthru structure 121*4882a593Smuzhiyun * @pthru_dma_h : dma handle for the passthru structure 122*4882a593Smuzhiyun * @epthru : extended passthru structure 123*4882a593Smuzhiyun * @epthru_dma_h : dma handle for extended passthru structure 124*4882a593Smuzhiyun * @buf_dma_h : dma handle for buffers w/o sg list 125*4882a593Smuzhiyun * 126*4882a593Smuzhiyun * command control block specific to the mailbox based controllers 127*4882a593Smuzhiyun */ 128*4882a593Smuzhiyun typedef struct { 129*4882a593Smuzhiyun uint8_t *raw_mbox; 130*4882a593Smuzhiyun mbox_t *mbox; 131*4882a593Smuzhiyun mbox64_t *mbox64; 132*4882a593Smuzhiyun dma_addr_t mbox_dma_h; 133*4882a593Smuzhiyun mbox_sgl64 *sgl64; 134*4882a593Smuzhiyun mbox_sgl32 *sgl32; 135*4882a593Smuzhiyun dma_addr_t sgl_dma_h; 136*4882a593Smuzhiyun mraid_passthru_t *pthru; 137*4882a593Smuzhiyun dma_addr_t pthru_dma_h; 138*4882a593Smuzhiyun mraid_epassthru_t *epthru; 139*4882a593Smuzhiyun dma_addr_t epthru_dma_h; 140*4882a593Smuzhiyun dma_addr_t buf_dma_h; 141*4882a593Smuzhiyun } mbox_ccb_t; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /** 145*4882a593Smuzhiyun * mraid_device_t - adapter soft state structure for mailbox controllers 146*4882a593Smuzhiyun * @una_mbox64 : 64-bit mbox - unaligned 147*4882a593Smuzhiyun * @una_mbox64_dma : mbox dma addr - unaligned 148*4882a593Smuzhiyun * @mbox : 32-bit mbox - aligned 149*4882a593Smuzhiyun * @mbox64 : 64-bit mbox - aligned 150*4882a593Smuzhiyun * @mbox_dma : mbox dma addr - aligned 151*4882a593Smuzhiyun * @mailbox_lock : exclusion lock for the mailbox 152*4882a593Smuzhiyun * @baseport : base port of hba memory 153*4882a593Smuzhiyun * @baseaddr : mapped addr of hba memory 154*4882a593Smuzhiyun * @mbox_pool : pool of mailboxes 155*4882a593Smuzhiyun * @mbox_pool_handle : handle for the mailbox pool memory 156*4882a593Smuzhiyun * @epthru_pool : a pool for extended passthru commands 157*4882a593Smuzhiyun * @epthru_pool_handle : handle to the pool above 158*4882a593Smuzhiyun * @sg_pool : pool of scatter-gather lists for this driver 159*4882a593Smuzhiyun * @sg_pool_handle : handle to the pool above 160*4882a593Smuzhiyun * @ccb_list : list of our command control blocks 161*4882a593Smuzhiyun * @uccb_list : list of cmd control blocks for mgmt module 162*4882a593Smuzhiyun * @umbox64 : array of mailbox for user commands (cmm) 163*4882a593Smuzhiyun * @pdrv_state : array for state of each physical drive. 164*4882a593Smuzhiyun * @last_disp : flag used to show device scanning 165*4882a593Smuzhiyun * @hw_error : set if FW not responding 166*4882a593Smuzhiyun * @fast_load : If set, skip physical device scanning 167*4882a593Smuzhiyun * @channel_class : channel class, RAID or SCSI 168*4882a593Smuzhiyun * @sysfs_mtx : mutex to serialize access to sysfs res. 169*4882a593Smuzhiyun * @sysfs_uioc : management packet to issue FW calls from sysfs 170*4882a593Smuzhiyun * @sysfs_mbox64 : mailbox packet to issue FW calls from sysfs 171*4882a593Smuzhiyun * @sysfs_buffer : data buffer for FW commands issued from sysfs 172*4882a593Smuzhiyun * @sysfs_buffer_dma : DMA buffer for FW commands issued from sysfs 173*4882a593Smuzhiyun * @sysfs_wait_q : wait queue for sysfs operations 174*4882a593Smuzhiyun * @random_del_supported : set if the random deletion is supported 175*4882a593Smuzhiyun * @curr_ldmap : current LDID map 176*4882a593Smuzhiyun * 177*4882a593Smuzhiyun * Initialization structure for mailbox controllers: memory based and IO based 178*4882a593Smuzhiyun * All the fields in this structure are LLD specific and may be discovered at 179*4882a593Smuzhiyun * init() or start() time. 180*4882a593Smuzhiyun * 181*4882a593Smuzhiyun * NOTE: The fields of this structures are placed to minimize cache misses 182*4882a593Smuzhiyun */ 183*4882a593Smuzhiyun #define MAX_LD_EXTENDED64 64 184*4882a593Smuzhiyun typedef struct { 185*4882a593Smuzhiyun mbox64_t *una_mbox64; 186*4882a593Smuzhiyun dma_addr_t una_mbox64_dma; 187*4882a593Smuzhiyun mbox_t *mbox; 188*4882a593Smuzhiyun mbox64_t *mbox64; 189*4882a593Smuzhiyun dma_addr_t mbox_dma; 190*4882a593Smuzhiyun spinlock_t mailbox_lock; 191*4882a593Smuzhiyun unsigned long baseport; 192*4882a593Smuzhiyun void __iomem * baseaddr; 193*4882a593Smuzhiyun struct mraid_pci_blk mbox_pool[MBOX_MAX_SCSI_CMDS]; 194*4882a593Smuzhiyun struct dma_pool *mbox_pool_handle; 195*4882a593Smuzhiyun struct mraid_pci_blk epthru_pool[MBOX_MAX_SCSI_CMDS]; 196*4882a593Smuzhiyun struct dma_pool *epthru_pool_handle; 197*4882a593Smuzhiyun struct mraid_pci_blk sg_pool[MBOX_MAX_SCSI_CMDS]; 198*4882a593Smuzhiyun struct dma_pool *sg_pool_handle; 199*4882a593Smuzhiyun mbox_ccb_t ccb_list[MBOX_MAX_SCSI_CMDS]; 200*4882a593Smuzhiyun mbox_ccb_t uccb_list[MBOX_MAX_USER_CMDS]; 201*4882a593Smuzhiyun mbox64_t umbox64[MBOX_MAX_USER_CMDS]; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun uint8_t pdrv_state[MBOX_MAX_PHYSICAL_DRIVES]; 204*4882a593Smuzhiyun uint32_t last_disp; 205*4882a593Smuzhiyun int hw_error; 206*4882a593Smuzhiyun int fast_load; 207*4882a593Smuzhiyun uint8_t channel_class; 208*4882a593Smuzhiyun struct mutex sysfs_mtx; 209*4882a593Smuzhiyun uioc_t *sysfs_uioc; 210*4882a593Smuzhiyun mbox64_t *sysfs_mbox64; 211*4882a593Smuzhiyun caddr_t sysfs_buffer; 212*4882a593Smuzhiyun dma_addr_t sysfs_buffer_dma; 213*4882a593Smuzhiyun wait_queue_head_t sysfs_wait_q; 214*4882a593Smuzhiyun int random_del_supported; 215*4882a593Smuzhiyun uint16_t curr_ldmap[MAX_LD_EXTENDED64]; 216*4882a593Smuzhiyun } mraid_device_t; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun // route to raid device from adapter 219*4882a593Smuzhiyun #define ADAP2RAIDDEV(adp) ((mraid_device_t *)((adp)->raid_device)) 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun #define MAILBOX_LOCK(rdev) (&(rdev)->mailbox_lock) 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun // Find out if this channel is a RAID or SCSI 224*4882a593Smuzhiyun #define IS_RAID_CH(rdev, ch) (((rdev)->channel_class >> (ch)) & 0x01) 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun #define RDINDOOR(rdev) readl((rdev)->baseaddr + 0x20) 228*4882a593Smuzhiyun #define RDOUTDOOR(rdev) readl((rdev)->baseaddr + 0x2C) 229*4882a593Smuzhiyun #define WRINDOOR(rdev, value) writel(value, (rdev)->baseaddr + 0x20) 230*4882a593Smuzhiyun #define WROUTDOOR(rdev, value) writel(value, (rdev)->baseaddr + 0x2C) 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun #endif // _MEGARAID_H_ 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun // vim: set ts=8 sw=8 tw=78: 235