Searched +full:imx8m +full:- +full:clock (Results 1 – 15 of 15) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Leonard Crestez <leonard.crestez@nxp.com>13 The i.MX SoC family has multiple buses for which clock frequency (and18 for normal (non-secure) world.20 The buses are based on externally licensed IPs such as ARM NIC-301 and27 - items:28 - enum:[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Leonard Crestez <leonard.crestez@nxp.com>18 switching is implemented by TF-A code which runs from a SRAM area.27 - enum:28 - fsl,imx8mn-ddrc29 - fsl,imx8mm-ddrc30 - fsl,imx8mq-ddrc[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/clock/imx8m-clock.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NXP i.MX8M Family Clock Control Module Binding10 - Anson Huang <Anson.Huang@nxp.com>13 NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock19 - fsl,imx8mm-ccm20 - fsl,imx8mn-ccm21 - fsl,imx8mp-ccm[all …]
1 // SPDX-License-Identifier: GPL-2.043 *freq = clk_get_rate(priv->clk); in imx_bus_get_cur_freq()53 stat->busy_time = 0; in imx_bus_get_dev_status()54 stat->total_time = 0; in imx_bus_get_dev_status()55 stat->current_frequency = clk_get_rate(priv->clk); in imx_bus_get_dev_status()65 platform_device_unregister(priv->icc_pdev); in imx_bus_exit()68 /* imx_bus_init_icc() - register matching icc provider if required */74 if (!of_get_property(dev->of_node, "#interconnect-cells", 0)) in imx_bus_init_icc()87 priv->icc_pdev = platform_device_register_data( in imx_bus_init_icc()88 dev, icc_driver_name, -1, NULL, 0); in imx_bus_init_icc()[all …]
1 // SPDX-License-Identifier: GPL-2.013 #include <linux/clk-provider.h>14 #include <linux/arm-smccc.h>40 * +----------+ |\ +------+41 * | dram_pll |-------|M| dram_core | |42 * +----------+ |U|---------->| D |43 * /--|X| | D |46 * +---------+ | |48 * +---------+ | |50 * +----------+ | | |[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Lucas Stach <l.stach@pengutronix.de>15 - const: fsl,imx-irqsteer16 - items:17 - const: fsl,imx8m-irqsteer18 - const: fsl,imx-irqsteer29 - description: output interrupt 0[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>7 #include <dt-bindings/clock/imx8mq-clock.h>8 #include <dt-bindings/power/imx8mq-power.h>9 #include <dt-bindings/reset/imx8mq-reset.h>10 #include <dt-bindings/gpio/gpio.h>11 #include "dt-bindings/input/input.h"12 #include <dt-bindings/interrupt-controller/arm-gic.h>13 #include <dt-bindings/thermal/thermal.h>14 #include "imx8mq-pinfunc.h"[all …]
1 // SPDX-License-Identifier: GPL-2.0+9 /dts-v1/;12 #include <dt-bindings/interrupt-controller/irq.h>15 model = "TechNexion PICO-PI-8M";16 compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";19 stdout-path = &uart1;22 pmic_osc: clock-pmic {23 compatible = "fixed-clock";24 #clock-cells = <0>;25 clock-frequency = <32768>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/imx8mn-clock.h>7 #include <dt-bindings/gpio/gpio.h>8 #include <dt-bindings/input/input.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/thermal/thermal.h>12 #include "imx8mn-pinfunc.h"15 interrupt-parent = <&gic>;16 #address-cells = <2>;17 #size-cells = <2>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/imx8mm-clock.h>7 #include <dt-bindings/gpio/gpio.h>8 #include <dt-bindings/input/input.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/thermal/thermal.h>12 #include "imx8mm-pinfunc.h"15 interrupt-parent = <&gic>;16 #address-cells = <2>;17 #size-cells = <2>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/imx8mp-clock.h>7 #include <dt-bindings/gpio/gpio.h>8 #include <dt-bindings/input/input.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/thermal/thermal.h>12 #include "imx8mp-pinfunc.h"15 interrupt-parent = <&gic>;16 #address-cells = <2>;17 #size-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.05 * This driver supports the fractional plls found in the imx8m SOCs8 * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=83411 #include <linux/clk-provider.h>48 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0, in clk_wait_lock()57 if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK)) in clk_wait_ack()61 return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0, in clk_wait_ack()70 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_prepare()72 writel_relaxed(val, pll->base + PLL_CFG0); in clk_pll_prepare()82 val = readl_relaxed(pll->base + PLL_CFG0); in clk_pll_unprepare()[all …]
1 // SPDX-License-Identifier: GPL-2.066 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},67 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},68 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},95 u32 quirks = pmu->devtype_data->quirks; in ddr_perf_filter_cap_get()117 int cap = (long)ea->var; in ddr_perf_filter_cap_show()147 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()169 return sprintf(page, "event=0x%02llx\n", pmu_attr->id); in ddr_pmu_event_show()181 IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04),182 IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05),[all …]
... arm926ejs/mxs/clock.c u-boot-2021.07/arch/arm/cpu/arm926ejs/ ...