1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale IRQSTEER Interrupt Multiplexer 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Lucas Stach <l.stach@pengutronix.de> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun oneOf: 15*4882a593Smuzhiyun - const: fsl,imx-irqsteer 16*4882a593Smuzhiyun - items: 17*4882a593Smuzhiyun - const: fsl,imx8m-irqsteer 18*4882a593Smuzhiyun - const: fsl,imx-irqsteer 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun maxItems: 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun interrupts: 24*4882a593Smuzhiyun description: | 25*4882a593Smuzhiyun should contain the up to 8 parent interrupt lines used to multiplex 26*4882a593Smuzhiyun the input interrupts. They should be specified sequentially from 27*4882a593Smuzhiyun output 0 to 7. 28*4882a593Smuzhiyun items: 29*4882a593Smuzhiyun - description: output interrupt 0 30*4882a593Smuzhiyun - description: output interrupt 1 31*4882a593Smuzhiyun - description: output interrupt 2 32*4882a593Smuzhiyun - description: output interrupt 3 33*4882a593Smuzhiyun - description: output interrupt 4 34*4882a593Smuzhiyun - description: output interrupt 5 35*4882a593Smuzhiyun - description: output interrupt 6 36*4882a593Smuzhiyun - description: output interrupt 7 37*4882a593Smuzhiyun minItems: 1 38*4882a593Smuzhiyun maxItems: 8 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun clocks: 41*4882a593Smuzhiyun maxItems: 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun clock-names: 44*4882a593Smuzhiyun const: ipg 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun interrupt-controller: true 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun "#interrupt-cells": 49*4882a593Smuzhiyun const: 1 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun fsl,channel: 52*4882a593Smuzhiyun $ref: '/schemas/types.yaml#/definitions/uint32' 53*4882a593Smuzhiyun description: | 54*4882a593Smuzhiyun u32 value representing the output channel that all input IRQs should be 55*4882a593Smuzhiyun steered into. 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun fsl,num-irqs: 58*4882a593Smuzhiyun $ref: '/schemas/types.yaml#/definitions/uint32' 59*4882a593Smuzhiyun description: | 60*4882a593Smuzhiyun u32 value representing the number of input interrupts of this channel, 61*4882a593Smuzhiyun should be multiple of 32 input interrupts and up to 512 interrupts. 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunrequired: 64*4882a593Smuzhiyun - compatible 65*4882a593Smuzhiyun - reg 66*4882a593Smuzhiyun - interrupts 67*4882a593Smuzhiyun - clocks 68*4882a593Smuzhiyun - clock-names 69*4882a593Smuzhiyun - interrupt-controller 70*4882a593Smuzhiyun - "#interrupt-cells" 71*4882a593Smuzhiyun - fsl,channel 72*4882a593Smuzhiyun - fsl,num-irqs 73*4882a593Smuzhiyun 74*4882a593SmuzhiyunadditionalProperties: false 75*4882a593Smuzhiyun 76*4882a593Smuzhiyunexamples: 77*4882a593Smuzhiyun - | 78*4882a593Smuzhiyun #include <dt-bindings/clock/imx8mq-clock.h> 79*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun interrupt-controller@32e2d000 { 82*4882a593Smuzhiyun compatible = "fsl,imx-irqsteer"; 83*4882a593Smuzhiyun reg = <0x32e2d000 0x1000>; 84*4882a593Smuzhiyun interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 85*4882a593Smuzhiyun clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; 86*4882a593Smuzhiyun clock-names = "ipg"; 87*4882a593Smuzhiyun fsl,channel = <0>; 88*4882a593Smuzhiyun fsl,num-irqs = <64>; 89*4882a593Smuzhiyun interrupt-controller; 90*4882a593Smuzhiyun #interrupt-cells = <1>; 91*4882a593Smuzhiyun }; 92