xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/imx8m-clock.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/imx8m-clock.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: NXP i.MX8M Family Clock Control Module Binding
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Anson Huang <Anson.Huang@nxp.com>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription: |
13*4882a593Smuzhiyun  NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock
14*4882a593Smuzhiyun  controller, which generates and supplies to all modules.
15*4882a593Smuzhiyun
16*4882a593Smuzhiyunproperties:
17*4882a593Smuzhiyun  compatible:
18*4882a593Smuzhiyun    enum:
19*4882a593Smuzhiyun      - fsl,imx8mm-ccm
20*4882a593Smuzhiyun      - fsl,imx8mn-ccm
21*4882a593Smuzhiyun      - fsl,imx8mp-ccm
22*4882a593Smuzhiyun      - fsl,imx8mq-ccm
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun  reg:
25*4882a593Smuzhiyun    maxItems: 1
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  clocks:
28*4882a593Smuzhiyun    minItems: 6
29*4882a593Smuzhiyun    maxItems: 7
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun  clock-names:
32*4882a593Smuzhiyun    minItems: 6
33*4882a593Smuzhiyun    maxItems: 7
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun  '#clock-cells':
36*4882a593Smuzhiyun    const: 1
37*4882a593Smuzhiyun    description:
38*4882a593Smuzhiyun      The clock consumer should specify the desired clock by having the clock
39*4882a593Smuzhiyun      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h
40*4882a593Smuzhiyun      for the full list of i.MX8M clock IDs.
41*4882a593Smuzhiyun
42*4882a593Smuzhiyunrequired:
43*4882a593Smuzhiyun  - compatible
44*4882a593Smuzhiyun  - reg
45*4882a593Smuzhiyun  - clocks
46*4882a593Smuzhiyun  - clock-names
47*4882a593Smuzhiyun  - '#clock-cells'
48*4882a593Smuzhiyun
49*4882a593SmuzhiyunallOf:
50*4882a593Smuzhiyun  - if:
51*4882a593Smuzhiyun      properties:
52*4882a593Smuzhiyun        compatible:
53*4882a593Smuzhiyun          contains:
54*4882a593Smuzhiyun            const: fsl,imx8mq-ccm
55*4882a593Smuzhiyun    then:
56*4882a593Smuzhiyun      properties:
57*4882a593Smuzhiyun        clocks:
58*4882a593Smuzhiyun          minItems: 7
59*4882a593Smuzhiyun          maxItems: 7
60*4882a593Smuzhiyun          items:
61*4882a593Smuzhiyun            - description: 32k osc
62*4882a593Smuzhiyun            - description: 25m osc
63*4882a593Smuzhiyun            - description: 27m osc
64*4882a593Smuzhiyun            - description: ext1 clock input
65*4882a593Smuzhiyun            - description: ext2 clock input
66*4882a593Smuzhiyun            - description: ext3 clock input
67*4882a593Smuzhiyun            - description: ext4 clock input
68*4882a593Smuzhiyun        clock-names:
69*4882a593Smuzhiyun          minItems: 7
70*4882a593Smuzhiyun          maxItems: 7
71*4882a593Smuzhiyun          items:
72*4882a593Smuzhiyun            - const: ckil
73*4882a593Smuzhiyun            - const: osc_25m
74*4882a593Smuzhiyun            - const: osc_27m
75*4882a593Smuzhiyun            - const: clk_ext1
76*4882a593Smuzhiyun            - const: clk_ext2
77*4882a593Smuzhiyun            - const: clk_ext3
78*4882a593Smuzhiyun            - const: clk_ext4
79*4882a593Smuzhiyun    else:
80*4882a593Smuzhiyun      properties:
81*4882a593Smuzhiyun        clocks:
82*4882a593Smuzhiyun          items:
83*4882a593Smuzhiyun            - description: 32k osc
84*4882a593Smuzhiyun            - description: 24m osc
85*4882a593Smuzhiyun            - description: ext1 clock input
86*4882a593Smuzhiyun            - description: ext2 clock input
87*4882a593Smuzhiyun            - description: ext3 clock input
88*4882a593Smuzhiyun            - description: ext4 clock input
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun        clock-names:
91*4882a593Smuzhiyun          items:
92*4882a593Smuzhiyun            - const: osc_32k
93*4882a593Smuzhiyun            - const: osc_24m
94*4882a593Smuzhiyun            - const: clk_ext1
95*4882a593Smuzhiyun            - const: clk_ext2
96*4882a593Smuzhiyun            - const: clk_ext3
97*4882a593Smuzhiyun            - const: clk_ext4
98*4882a593Smuzhiyun
99*4882a593SmuzhiyunadditionalProperties: false
100*4882a593Smuzhiyun
101*4882a593Smuzhiyunexamples:
102*4882a593Smuzhiyun  # Clock Control Module node:
103*4882a593Smuzhiyun  - |
104*4882a593Smuzhiyun    clock-controller@30380000 {
105*4882a593Smuzhiyun        compatible = "fsl,imx8mm-ccm";
106*4882a593Smuzhiyun        reg = <0x30380000 0x10000>;
107*4882a593Smuzhiyun        #clock-cells = <1>;
108*4882a593Smuzhiyun        clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
109*4882a593Smuzhiyun                 <&clk_ext3>, <&clk_ext4>;
110*4882a593Smuzhiyun        clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
111*4882a593Smuzhiyun                      "clk_ext3", "clk_ext4";
112*4882a593Smuzhiyun    };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun  - |
115*4882a593Smuzhiyun    clock-controller@30390000 {
116*4882a593Smuzhiyun        compatible = "fsl,imx8mq-ccm";
117*4882a593Smuzhiyun        reg = <0x30380000 0x10000>;
118*4882a593Smuzhiyun        #clock-cells = <1>;
119*4882a593Smuzhiyun        clocks = <&ckil>, <&osc_25m>, <&osc_27m>, <&clk_ext1>,
120*4882a593Smuzhiyun                 <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
121*4882a593Smuzhiyun        clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1",
122*4882a593Smuzhiyun                      "clk_ext2", "clk_ext3", "clk_ext4";
123*4882a593Smuzhiyun    };
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun...
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