Searched +full:ast2500 +full:- +full:lpc +full:- +full:host (Results 1 – 20 of 20) sorted by relevance
2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth7 primary use case of the Aspeed LPC controller is as a slave on the bus11 The LPC controller is represented as a multi-function device to account for the14 "basically compatible with the [LPC registers from the] popular BMC controller17 here labeled the "host" portion of the controller, includes, but is not limited22 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the23 physical properties of some LPC pins, configuration of serial IRQs, and24 APB-to-LPC bridging amonst other functions.26 * An LPC Host Interface Controller: Manages functions exposed to the host such[all …]
3 The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs5 used to perform in-band IPMI communication with their host.9 - compatible : should be one of10 "aspeed,ast2400-kcs-bmc"11 "aspeed,ast2500-kcs-bmc"12 - interrupts : interrupt generated by the controller13 - kcs_chan : The LPC channel number in the controller14 - kcs_addr : The host CPU IO map address18 - compatible : should be one of19 "aspeed,ast2400-kcs-bmc-v2"[all …]
1 # SPDX-License-Identifier: GPL-2.0-or-later3 ---4 $id: http://devicetree.org/schemas/pinctrl/aspeed,ast2500-pinctrl.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: ASPEED AST2500 Pin Controller10 - Andrew Jeffery <andrew@aj.id.au>16 - compatible: Should be one of the following:17 "aspeed,ast2500-scu", "syscon", "simple-mfd"18 "aspeed,g5-scu", "syscon", "simple-mfd"25 const: aspeed,ast2500-pinctrl[all …]
1 # SPDX-License-Identifier: GPL-2.0-only10 tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"12 Control Aspeed ast2400/2500 HOST LPC to BMC mappings through14 region where the host LPC read/write region can be buffered.17 tristate "Aspeed ast2500 HOST LPC snoop support"20 Provides a driver to control the LPC snoop interface which22 the host to an arbitrary LPC I/O port.26 tristate "Aspeed ast2400/2500 HOST P2A VGA MMIO to BMC bridge control"28 Control Aspeed ast2400/2500 HOST P2A VGA MMIO to BMC mappings through30 a pre-defined region.
1 // SPDX-License-Identifier: GPL-2.0-or-later5 * Provides a simple driver to control the ASPEED LPC snoop interface which7 * the host to an arbitrary LPC I/O port.9 * Typically used by the BMC to "watch" host boot progress via port27 #define DEVICE_NAME "aspeed-lpc-snoop"56 /* The ast2400 has bits 14 and 15 as reserved, whereas the ast250077 return container_of(file->private_data, in snoop_file_to_chan()89 if (kfifo_is_empty(&chan->fifo)) { in snoop_file_read()90 if (file->f_flags & O_NONBLOCK) in snoop_file_read()91 return -EAGAIN; in snoop_file_read()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later16 #include <linux/aspeed-lpc-ctrl.h>18 #define DEVICE_NAME "aspeed-lpc-ctrl"39 return container_of(file->private_data, struct aspeed_lpc_ctrl, in file_aspeed_lpc_ctrl()46 unsigned long vsize = vma->vm_end - vma->vm_start; in aspeed_lpc_ctrl_mmap()47 pgprot_t prot = vma->vm_page_prot; in aspeed_lpc_ctrl_mmap()49 if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT) in aspeed_lpc_ctrl_mmap()50 return -EINVAL; in aspeed_lpc_ctrl_mmap()55 if (remap_pfn_range(vma, vma->vm_start, in aspeed_lpc_ctrl_mmap()56 (lpc_ctrl->mem_base >> PAGE_SHIFT) + vma->vm_pgoff, in aspeed_lpc_ctrl_mmap()[all …]
1 // SPDX-License-Identifier: GPL-2.0+2 #include <dt-bindings/clock/aspeed-clock.h>3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>7 compatible = "aspeed,ast2500";8 #address-cells = <1>;9 #size-cells = <1>;10 interrupt-parent = <&vic>;36 #address-cells = <1>;37 #size-cells = <0>;40 compatible = "arm,arm1176jzf-s";[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>6 #include <dt-bindings/clock/ast2600-clock.h>11 #address-cells = <1>;12 #size-cells = <1>;13 interrupt-parent = <&gic>;43 #address-cells = <1>;44 #size-cells = <0>;45 enable-method = "aspeed,ast2600-smp";[all …]
1 // SPDX-License-Identifier: GPL-2.04 /dts-v1/;6 #include "aspeed-g5.dtsi"7 #include <dt-bindings/gpio/aspeed-gpio.h>11 compatible = "amd,ethanolx-bmc", "aspeed,ast2500";21 stdout-path = &uart5;25 compatible = "gpio-leds";35 iio-hwmon {36 compatible = "iio-hwmon";37 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+4 /dts-v1/;6 #include "aspeed-g5.dtsi"7 #include <dt-bindings/gpio/aspeed-gpio.h>8 #include <dt-bindings/i2c/i2c.h>12 compatible = "facebook,tiogapass-bmc", "aspeed,ast2500";39 stdout-path = &uart5;47 iio-hwmon {48 compatible = "iio-hwmon";49 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,[all …]
3 * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi9 compatible = "aspeed,ast2500";10 #address-cells = <1>;11 #size-cells = <1>;12 interrupt-parent = <&vic>;15 #address-cells = <1>;16 #size-cells = <0>;19 compatible = "arm,arm1176jzf-s";26 compatible = "simple-bus";27 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (c) 2015-2018, Intel Corporation.6 #define pr_fmt(fmt) "aspeed-kcs-bmc: " fmt26 #define DEVICE_NAME "ast-kcs-bmc"30 /* mapped to lpc-bmc@0 IO space */56 /* mapped to lpc-host@80 IO space */76 rc = regmap_read(priv->map, reg, &val); in aspeed_kcs_inb()87 rc = regmap_write(priv->map, reg, data); in aspeed_kcs_outb()109 switch (kcs_bmc->channel) { in aspeed_kcs_set_address()111 regmap_update_bits(priv->map, LPC_HICR4, in aspeed_kcs_set_address()[all …]
1 // SPDX-License-Identifier: GPL-2.0+4 #define pr_fmt(fmt) "clk-aspeed: " fmt13 #include <dt-bindings/clock/aspeed-clock.h>15 #include "clk-aspeed.h"49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */[all …]
1 # SPDX-License-Identifier: GPL-2.0-only8 in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips,10 the host firmware. The implementation only supports SPI NOR.24 Enable support for the NXP LPC SPI Flash Interface controller.47 will be called intel-spi-pci.64 will be called intel-spi-platform.
23 Enable old-style I2C functions for compatibility with existing code.35 I2C or LPC). Some Chromebooks use this when the hardware design41 ---help---43 often dealt with by using an I2C pass-through interface provided by44 the EC. On some unfortunate models (e.g. Spring) the pass-through71 configuration is given by the device tree. Kernel-style device tree73 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt82 i2c-gpio driver unless your system can cope with this limitation.83 Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt96 Say yes here to select Cadence I2C Host Controller. This controller is[all …]
1 // SPDX-License-Identifier: GPL-2.0+50 * controller) and one is on the host CPU side.52 * It allows the BMC to provide to the host a "UART" that pipes into58 * at what IO port and interrupt number the host side will appear59 * to the host on the Host <-> BMC LPC bus. It could be different on a69 addr = (readb(vuart->regs + ASPEED_VUART_ADDRH) << 8) | in lpc_address_show()70 (readb(vuart->regs + ASPEED_VUART_ADDRL)); in lpc_address_show()72 return snprintf(buf, PAGE_SIZE - 1, "0x%x\n", addr); in lpc_address_show()87 writeb(val >> 8, vuart->regs + ASPEED_VUART_ADDRH); in lpc_address_store()88 writeb(val >> 0, vuart->regs + ASPEED_VUART_ADDRL); in lpc_address_store()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only20 sensors-detect script from the lm_sensors package. Read21 <file:Documentation/hwmon/userspace-tools.rst> for details.52 will be called abx500-temp.267 will be called as370-hwmon.290 will be called axi-fan-control299 lm-sensors 2.10.1 for proper userspace support.348 Only Intel-based Apple's computers are supported (MacBook Pro,355 the laptop to act as a pinball machine-esque joystick.370 will be called scmi-hwmon.[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later16 #include <linux/pinctrl/pinconf-generic.h>21 #include "../pinctrl-utils.h"22 #include "pinctrl-aspeed.h"32 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet35 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions37 * reset control and MAC clock configuration registers. The AST2500 goes a step45 #define SCU80 0x80 /* Multi-function Pin Control #1 */46 #define SCU84 0x84 /* Multi-function Pin Control #2 */47 #define SCU88 0x88 /* Multi-function Pin Control #3 */[all …]
... -boot-2021.07/.readthedocs.yml u-boot-2021.07/Kbuild u-boot-2021.07 ...
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]