xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun// Copyright (c) 2020 AMD Inc.
3*4882a593Smuzhiyun// Author: Supreeth Venkatesh <supreeth.venkatesh@amd.com>
4*4882a593Smuzhiyun/dts-v1/;
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include "aspeed-g5.dtsi"
7*4882a593Smuzhiyun#include <dt-bindings/gpio/aspeed-gpio.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	model = "AMD EthanolX BMC";
11*4882a593Smuzhiyun	compatible = "amd,ethanolx-bmc", "aspeed,ast2500";
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	memory@80000000 {
14*4882a593Smuzhiyun		reg = <0x80000000 0x20000000>;
15*4882a593Smuzhiyun	};
16*4882a593Smuzhiyun	aliases {
17*4882a593Smuzhiyun		serial0 = &uart1;
18*4882a593Smuzhiyun		serial4 = &uart5;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun	chosen {
21*4882a593Smuzhiyun		stdout-path = &uart5;
22*4882a593Smuzhiyun		bootargs = "console=ttyS4,115200 earlyprintk";
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun	leds {
25*4882a593Smuzhiyun		compatible = "gpio-leds";
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		fault {
28*4882a593Smuzhiyun			gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
29*4882a593Smuzhiyun		};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun		identify {
32*4882a593Smuzhiyun			gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>;
33*4882a593Smuzhiyun		};
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun	iio-hwmon {
36*4882a593Smuzhiyun		compatible = "iio-hwmon";
37*4882a593Smuzhiyun		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun&fmc {
42*4882a593Smuzhiyun	status = "okay";
43*4882a593Smuzhiyun	flash@0 {
44*4882a593Smuzhiyun		status = "okay";
45*4882a593Smuzhiyun		m25p,fast-read;
46*4882a593Smuzhiyun		#include "openbmc-flash-layout.dtsi"
47*4882a593Smuzhiyun	};
48*4882a593Smuzhiyun};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun&mac0 {
52*4882a593Smuzhiyun	status = "okay";
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	pinctrl-names = "default";
55*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_rmii1_default>;
56*4882a593Smuzhiyun	clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
57*4882a593Smuzhiyun		 <&syscon ASPEED_CLK_MAC1RCLK>;
58*4882a593Smuzhiyun	clock-names = "MACCLK", "RCLK";
59*4882a593Smuzhiyun};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun&uart1 {
62*4882a593Smuzhiyun	//Host Console
63*4882a593Smuzhiyun	status = "okay";
64*4882a593Smuzhiyun	pinctrl-names = "default";
65*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_txd1_default
66*4882a593Smuzhiyun		     &pinctrl_rxd1_default>;
67*4882a593Smuzhiyun};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun&uart5 {
70*4882a593Smuzhiyun	//BMC Console
71*4882a593Smuzhiyun	status = "okay";
72*4882a593Smuzhiyun};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun&adc {
75*4882a593Smuzhiyun	status = "okay";
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun	pinctrl-names = "default";
78*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_adc0_default
79*4882a593Smuzhiyun		     &pinctrl_adc1_default
80*4882a593Smuzhiyun		     &pinctrl_adc2_default
81*4882a593Smuzhiyun		     &pinctrl_adc3_default
82*4882a593Smuzhiyun		     &pinctrl_adc4_default>;
83*4882a593Smuzhiyun};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun//APML for P0
86*4882a593Smuzhiyun&i2c0 {
87*4882a593Smuzhiyun	status = "okay";
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun//APML for P1
91*4882a593Smuzhiyun&i2c1 {
92*4882a593Smuzhiyun	status = "okay";
93*4882a593Smuzhiyun};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun// Thermal Sensors
96*4882a593Smuzhiyun&i2c7 {
97*4882a593Smuzhiyun	status = "okay";
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun	lm75a@48 {
100*4882a593Smuzhiyun		compatible = "national,lm75a";
101*4882a593Smuzhiyun		reg = <0x48>;
102*4882a593Smuzhiyun	};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun	lm75a@49 {
105*4882a593Smuzhiyun		compatible = "national,lm75a";
106*4882a593Smuzhiyun		reg = <0x49>;
107*4882a593Smuzhiyun	};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun	lm75a@4a {
110*4882a593Smuzhiyun		compatible = "national,lm75a";
111*4882a593Smuzhiyun		reg = <0x4a>;
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun	lm75a@4b {
115*4882a593Smuzhiyun		compatible = "national,lm75a";
116*4882a593Smuzhiyun		reg = <0x4b>;
117*4882a593Smuzhiyun	};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun	lm75a@4c {
120*4882a593Smuzhiyun		compatible = "national,lm75a";
121*4882a593Smuzhiyun		reg = <0x4c>;
122*4882a593Smuzhiyun	};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	lm75a@4d {
125*4882a593Smuzhiyun		compatible = "national,lm75a";
126*4882a593Smuzhiyun		reg = <0x4d>;
127*4882a593Smuzhiyun	};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun	lm75a@4e {
130*4882a593Smuzhiyun		compatible = "national,lm75a";
131*4882a593Smuzhiyun		reg = <0x4e>;
132*4882a593Smuzhiyun	};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun	lm75a@4f {
135*4882a593Smuzhiyun		compatible = "national,lm75a";
136*4882a593Smuzhiyun		reg = <0x4f>;
137*4882a593Smuzhiyun	};
138*4882a593Smuzhiyun};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun&kcs1 {
141*4882a593Smuzhiyun	status = "okay";
142*4882a593Smuzhiyun	kcs_addr = <0x60>;
143*4882a593Smuzhiyun};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun&kcs2 {
146*4882a593Smuzhiyun	status = "okay";
147*4882a593Smuzhiyun	kcs_addr = <0x62>;
148*4882a593Smuzhiyun};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&kcs4 {
151*4882a593Smuzhiyun	status = "okay";
152*4882a593Smuzhiyun	kcs_addr = <0x97DE>;
153*4882a593Smuzhiyun};
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun&lpc_snoop {
156*4882a593Smuzhiyun	status = "okay";
157*4882a593Smuzhiyun	snoop-ports = <0x80>;
158*4882a593Smuzhiyun};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun&lpc_ctrl {
161*4882a593Smuzhiyun	//Enable lpc clock
162*4882a593Smuzhiyun	status = "okay";
163*4882a593Smuzhiyun};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun&pwm_tacho {
166*4882a593Smuzhiyun	status = "okay";
167*4882a593Smuzhiyun	pinctrl-names = "default";
168*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm0_default
169*4882a593Smuzhiyun	&pinctrl_pwm1_default
170*4882a593Smuzhiyun	&pinctrl_pwm2_default
171*4882a593Smuzhiyun	&pinctrl_pwm3_default
172*4882a593Smuzhiyun	&pinctrl_pwm4_default
173*4882a593Smuzhiyun	&pinctrl_pwm5_default
174*4882a593Smuzhiyun	&pinctrl_pwm6_default
175*4882a593Smuzhiyun	&pinctrl_pwm7_default>;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun	fan@0 {
178*4882a593Smuzhiyun		reg = <0x00>;
179*4882a593Smuzhiyun		aspeed,fan-tach-ch = /bits/ 8 <0x00>;
180*4882a593Smuzhiyun	};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	fan@1 {
183*4882a593Smuzhiyun		reg = <0x01>;
184*4882a593Smuzhiyun		aspeed,fan-tach-ch = /bits/ 8 <0x01>;
185*4882a593Smuzhiyun	};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun	fan@2 {
188*4882a593Smuzhiyun		reg = <0x02>;
189*4882a593Smuzhiyun		aspeed,fan-tach-ch = /bits/ 8 <0x02>;
190*4882a593Smuzhiyun	};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun	fan@3 {
193*4882a593Smuzhiyun		reg = <0x03>;
194*4882a593Smuzhiyun		aspeed,fan-tach-ch = /bits/ 8 <0x03>;
195*4882a593Smuzhiyun	};
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun	fan@4 {
198*4882a593Smuzhiyun		reg = <0x04>;
199*4882a593Smuzhiyun		aspeed,fan-tach-ch = /bits/ 8 <0x04>;
200*4882a593Smuzhiyun	};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun	fan@5 {
203*4882a593Smuzhiyun		reg = <0x05>;
204*4882a593Smuzhiyun		aspeed,fan-tach-ch = /bits/ 8 <0x05>;
205*4882a593Smuzhiyun	};
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun	fan@6 {
208*4882a593Smuzhiyun		reg = <0x06>;
209*4882a593Smuzhiyun		aspeed,fan-tach-ch = /bits/ 8 <0x06>;
210*4882a593Smuzhiyun	};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun	fan@7 {
213*4882a593Smuzhiyun		reg = <0x07>;
214*4882a593Smuzhiyun		aspeed,fan-tach-ch = /bits/ 8 <0x07>;
215*4882a593Smuzhiyun	};
216*4882a593Smuzhiyun};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun
220