1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun// Copyright (c) 2018 Facebook Inc. 3*4882a593Smuzhiyun// Author: Vijay Khemka <vijaykhemka@fb.com> 4*4882a593Smuzhiyun/dts-v1/; 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "aspeed-g5.dtsi" 7*4882a593Smuzhiyun#include <dt-bindings/gpio/aspeed-gpio.h> 8*4882a593Smuzhiyun#include <dt-bindings/i2c/i2c.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Facebook TiogaPass BMC"; 12*4882a593Smuzhiyun compatible = "facebook,tiogapass-bmc", "aspeed,ast2500"; 13*4882a593Smuzhiyun aliases { 14*4882a593Smuzhiyun serial0 = &uart1; 15*4882a593Smuzhiyun serial4 = &uart5; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * Hardcode the bus number of i2c switches' channels to 19*4882a593Smuzhiyun * avoid breaking the legacy applications. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun i2c16 = &imux16; 22*4882a593Smuzhiyun i2c17 = &imux17; 23*4882a593Smuzhiyun i2c18 = &imux18; 24*4882a593Smuzhiyun i2c19 = &imux19; 25*4882a593Smuzhiyun i2c20 = &imux20; 26*4882a593Smuzhiyun i2c21 = &imux21; 27*4882a593Smuzhiyun i2c22 = &imux22; 28*4882a593Smuzhiyun i2c23 = &imux23; 29*4882a593Smuzhiyun i2c24 = &imux24; 30*4882a593Smuzhiyun i2c25 = &imux25; 31*4882a593Smuzhiyun i2c26 = &imux26; 32*4882a593Smuzhiyun i2c27 = &imux27; 33*4882a593Smuzhiyun i2c28 = &imux28; 34*4882a593Smuzhiyun i2c29 = &imux29; 35*4882a593Smuzhiyun i2c30 = &imux30; 36*4882a593Smuzhiyun i2c31 = &imux31; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun chosen { 39*4882a593Smuzhiyun stdout-path = &uart5; 40*4882a593Smuzhiyun bootargs = "console=ttyS4,115200 earlyprintk"; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun memory@80000000 { 44*4882a593Smuzhiyun reg = <0x80000000 0x20000000>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun iio-hwmon { 48*4882a593Smuzhiyun compatible = "iio-hwmon"; 49*4882a593Smuzhiyun io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, 50*4882a593Smuzhiyun <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun}; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun&fmc { 56*4882a593Smuzhiyun status = "okay"; 57*4882a593Smuzhiyun flash@0 { 58*4882a593Smuzhiyun status = "okay"; 59*4882a593Smuzhiyun m25p,fast-read; 60*4882a593Smuzhiyun#include "openbmc-flash-layout.dtsi" 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun}; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun&spi1 { 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun pinctrl-names = "default"; 67*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_spi1_default>; 68*4882a593Smuzhiyun flash@0 { 69*4882a593Smuzhiyun status = "okay"; 70*4882a593Smuzhiyun m25p,fast-read; 71*4882a593Smuzhiyun label = "pnor"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun}; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&lpc_snoop { 76*4882a593Smuzhiyun status = "okay"; 77*4882a593Smuzhiyun snoop-ports = <0x80>; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&lpc_ctrl { 81*4882a593Smuzhiyun // Enable lpc clock 82*4882a593Smuzhiyun status = "okay"; 83*4882a593Smuzhiyun}; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun&uart1 { 86*4882a593Smuzhiyun // Host Console 87*4882a593Smuzhiyun status = "okay"; 88*4882a593Smuzhiyun pinctrl-names = "default"; 89*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_txd1_default 90*4882a593Smuzhiyun &pinctrl_rxd1_default>; 91*4882a593Smuzhiyun}; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun&uart2 { 94*4882a593Smuzhiyun // SoL Host Console 95*4882a593Smuzhiyun status = "okay"; 96*4882a593Smuzhiyun}; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun&uart3 { 99*4882a593Smuzhiyun // SoL BMC Console 100*4882a593Smuzhiyun status = "okay"; 101*4882a593Smuzhiyun}; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun&uart5 { 104*4882a593Smuzhiyun // BMC Console 105*4882a593Smuzhiyun status = "okay"; 106*4882a593Smuzhiyun}; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun&kcs2 { 109*4882a593Smuzhiyun // BMC KCS channel 2 110*4882a593Smuzhiyun status = "okay"; 111*4882a593Smuzhiyun aspeed,lpc-io-reg = <0xca8>; 112*4882a593Smuzhiyun}; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun&kcs3 { 115*4882a593Smuzhiyun // BMC KCS channel 3 116*4882a593Smuzhiyun status = "okay"; 117*4882a593Smuzhiyun aspeed,lpc-io-reg = <0xca2>; 118*4882a593Smuzhiyun}; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun&gpio { 121*4882a593Smuzhiyun status = "okay"; 122*4882a593Smuzhiyun gpio-line-names = 123*4882a593Smuzhiyun /*A0-A7*/ "BMC_CPLD_FPGA_SEL","","","","","","","", 124*4882a593Smuzhiyun /*B0-B7*/ "","BMC_DEBUG_EN","","","","BMC_PPIN","PS_PWROK", 125*4882a593Smuzhiyun "IRQ_PVDDQ_GHJ_VRHOT_LVT3", 126*4882a593Smuzhiyun /*C0-C7*/ "","","","","","","","", 127*4882a593Smuzhiyun /*D0-D7*/ "BIOS_MRC_DEBUG_MSG_DIS","BOARD_REV_ID0","", 128*4882a593Smuzhiyun "BOARD_REV_ID1","IRQ_DIMM_SAVE_LVT3","BOARD_REV_ID2", 129*4882a593Smuzhiyun "CPU_ERR0_LVT3_BMC","CPU_ERR1_LVT3_BMC", 130*4882a593Smuzhiyun /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON", 131*4882a593Smuzhiyun "POWER_OUT","NMI_BUTTON","","CPU0_PROCHOT_LVT3_ BMC", 132*4882a593Smuzhiyun "CPU1_PROCHOT_LVT3_ BMC", 133*4882a593Smuzhiyun /*F0-F7*/ "IRQ_PVDDQ_ABC_VRHOT_LVT3","", 134*4882a593Smuzhiyun "IRQ_PVCCIN_CPU0_VRHOT_LVC3", 135*4882a593Smuzhiyun "IRQ_PVCCIN_CPU1_VRHOT_LVC3", 136*4882a593Smuzhiyun "IRQ_PVDDQ_KLM_VRHOT_LVT3","","P3VBAT_BRIDGE_EN","", 137*4882a593Smuzhiyun /*G0-G7*/ "CPU_ERR2_LVT3","CPU_CATERR_LVT3","PCH_BMC_THERMTRIP", 138*4882a593Smuzhiyun "CPU0_SKTOCC_LVT3","","","","BIOS_SMI_ACTIVE", 139*4882a593Smuzhiyun /*H0-H7*/ "LED_POST_CODE_0","LED_POST_CODE_1","LED_POST_CODE_2", 140*4882a593Smuzhiyun "LED_POST_CODE_3","LED_POST_CODE_4","LED_POST_CODE_5", 141*4882a593Smuzhiyun "LED_POST_CODE_6","LED_POST_CODE_7", 142*4882a593Smuzhiyun /*I0-I7*/ "CPU0_FIVR_FAULT_LVT3","CPU1_FIVR_FAULT_LVT3", 143*4882a593Smuzhiyun "FORCE_ADR","UV_ADR_TRIGGER_EN","","","","", 144*4882a593Smuzhiyun /*J0-J7*/ "","","","","","","","", 145*4882a593Smuzhiyun /*K0-K7*/ "","","","","","","","", 146*4882a593Smuzhiyun /*L0-L7*/ "IRQ_UV_DETECT","IRQ_OC_DETECT","HSC_TIMER_EXP","", 147*4882a593Smuzhiyun "MEM_THERM_EVENT_PCH","PMBUS_ALERT_BUF_EN","","", 148*4882a593Smuzhiyun /*M0-M7*/ "CPU0_RC_ERROR","CPU1_RC_ERROR","","OC_DETECT_EN", 149*4882a593Smuzhiyun "CPU0_THERMTRIP_LATCH_LVT3", 150*4882a593Smuzhiyun "CPU1_THERMTRIP_LATCH_LVT3","","", 151*4882a593Smuzhiyun /*N0-N7*/ "","","","CPU_MSMI_LVT3","","BIOS_SPI_BMC_CTRL","","", 152*4882a593Smuzhiyun /*O0-O7*/ "","","","","","","","", 153*4882a593Smuzhiyun /*P0-P7*/ "BOARD_SKU_ID0","BOARD_SKU_ID1","BOARD_SKU_ID2", 154*4882a593Smuzhiyun "BOARD_SKU_ID3","BOARD_SKU_ID4","BMC_PREQ", 155*4882a593Smuzhiyun "BMC_PWR_DEBUG","RST_RSMRST", 156*4882a593Smuzhiyun /*Q0-Q7*/ "","","","","UARTSW_LSB","UARTSW_MSB", 157*4882a593Smuzhiyun "POST_CARD_PRES_BMC","PE_BMC_WAKE", 158*4882a593Smuzhiyun /*R0-R7*/ "","","BMC_TCK_MUX_SEL","BMC_PRDY", 159*4882a593Smuzhiyun "BMC_XDP_PRSNT_IN","RST_BMC_PLTRST_BUF","SLT_CFG0", 160*4882a593Smuzhiyun "SLT_CFG1", 161*4882a593Smuzhiyun /*S0-S7*/ "THROTTLE","BMC_READY","","HSC_SMBUS_SWITCH_EN","", 162*4882a593Smuzhiyun "","","", 163*4882a593Smuzhiyun /*T0-T7*/ "","","","","","","","", 164*4882a593Smuzhiyun /*U0-U7*/ "","","","","","BMC_FAULT","","", 165*4882a593Smuzhiyun /*V0-V7*/ "","","","FAST_PROCHOT_EN","","","","", 166*4882a593Smuzhiyun /*W0-W7*/ "","","","","","","","", 167*4882a593Smuzhiyun /*X0-X7*/ "","","","GLOBAL_RST_WARN", 168*4882a593Smuzhiyun "CPU0_MEMABC_MEMHOT_LVT3_BMC", 169*4882a593Smuzhiyun "CPU0_MEMDEF_MEMHOT_LVT3_BMC", 170*4882a593Smuzhiyun "CPU1_MEMGHJ_MEMHOT_LVT3_BMC", 171*4882a593Smuzhiyun "CPU1_MEMKLM_MEMHOT_LVT3_BMC", 172*4882a593Smuzhiyun /*Y0-Y7*/ "SIO_S3","SIO_S5","BMC_JTAG_SEL","SIO_ONCONTROL","", 173*4882a593Smuzhiyun "","","", 174*4882a593Smuzhiyun /*Z0-Z7*/ "","SIO_POWER_GOOD","IRQ_PVDDQ_DEF_VRHOT_LVT3","", 175*4882a593Smuzhiyun "","","","", 176*4882a593Smuzhiyun /*AA0-AA7*/ "CPU1_SKTOCC_LVT3","IRQ_SML1_PMBUS_ALERT", 177*4882a593Smuzhiyun "SERVER_POWER_LED","","PECI_MUX_SELECT","UV_HIGH_SET", 178*4882a593Smuzhiyun "","POST_COMPLETE", 179*4882a593Smuzhiyun /*AB0-AB7*/ "IRQ_HSC_FAULT","OCP_MEZZA_PRES","","","","","","", 180*4882a593Smuzhiyun /*AC0-AC7*/ "","","","","","","",""; 181*4882a593Smuzhiyun}; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun&mac0 { 184*4882a593Smuzhiyun status = "okay"; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun pinctrl-names = "default"; 187*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_rmii1_default>; 188*4882a593Smuzhiyun clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, 189*4882a593Smuzhiyun <&syscon ASPEED_CLK_MAC1RCLK>; 190*4882a593Smuzhiyun clock-names = "MACCLK", "RCLK"; 191*4882a593Smuzhiyun use-ncsi; 192*4882a593Smuzhiyun}; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun&adc { 195*4882a593Smuzhiyun status = "okay"; 196*4882a593Smuzhiyun}; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun&i2c0 { 199*4882a593Smuzhiyun status = "okay"; 200*4882a593Smuzhiyun //Airmax Conn B, CPU0 PIROM, CPU1 PIROM 201*4882a593Smuzhiyun}; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun&i2c1 { 204*4882a593Smuzhiyun status = "okay"; 205*4882a593Smuzhiyun //X24 Riser 206*4882a593Smuzhiyun i2c-switch@71 { 207*4882a593Smuzhiyun compatible = "nxp,pca9544"; 208*4882a593Smuzhiyun #address-cells = <1>; 209*4882a593Smuzhiyun #size-cells = <0>; 210*4882a593Smuzhiyun reg = <0x71>; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun imux16: i2c@0 { 213*4882a593Smuzhiyun #address-cells = <1>; 214*4882a593Smuzhiyun #size-cells = <0>; 215*4882a593Smuzhiyun reg = <0>; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun ina230@45 { 218*4882a593Smuzhiyun compatible = "ti,ina230"; 219*4882a593Smuzhiyun reg = <0x45>; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun tmp75@48 { 223*4882a593Smuzhiyun compatible = "ti,tmp75"; 224*4882a593Smuzhiyun reg = <0x48>; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun tmp421@49 { 228*4882a593Smuzhiyun compatible = "ti,tmp75"; 229*4882a593Smuzhiyun reg = <0x49>; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun eeprom@50 { 233*4882a593Smuzhiyun compatible = "atmel,24c64"; 234*4882a593Smuzhiyun reg = <0x50>; 235*4882a593Smuzhiyun pagesize = <32>; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun i2c-switch@73 { 239*4882a593Smuzhiyun compatible = "nxp,pca9546"; 240*4882a593Smuzhiyun #address-cells = <1>; 241*4882a593Smuzhiyun #size-cells = <0>; 242*4882a593Smuzhiyun reg = <0x73>; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun imux20: i2c@0 { 245*4882a593Smuzhiyun #address-cells = <1>; 246*4882a593Smuzhiyun #size-cells = <0>; 247*4882a593Smuzhiyun reg = <0>; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun imux21: i2c@1 { 251*4882a593Smuzhiyun #address-cells = <1>; 252*4882a593Smuzhiyun #size-cells = <0>; 253*4882a593Smuzhiyun reg = <1>; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun imux22: i2c@2 { 257*4882a593Smuzhiyun #address-cells = <1>; 258*4882a593Smuzhiyun #size-cells = <0>; 259*4882a593Smuzhiyun reg = <2>; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun imux23: i2c@3 { 263*4882a593Smuzhiyun #address-cells = <1>; 264*4882a593Smuzhiyun #size-cells = <0>; 265*4882a593Smuzhiyun reg = <3>; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun imux17: i2c@1 { 273*4882a593Smuzhiyun #address-cells = <1>; 274*4882a593Smuzhiyun #size-cells = <0>; 275*4882a593Smuzhiyun reg = <1>; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun ina230@45 { 278*4882a593Smuzhiyun compatible = "ti,ina230"; 279*4882a593Smuzhiyun reg = <0x45>; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun tmp421@48 { 283*4882a593Smuzhiyun compatible = "ti,tmp75"; 284*4882a593Smuzhiyun reg = <0x48>; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun tmp421@49 { 288*4882a593Smuzhiyun compatible = "ti,tmp75"; 289*4882a593Smuzhiyun reg = <0x49>; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun eeprom@50 { 293*4882a593Smuzhiyun compatible = "atmel,24c64"; 294*4882a593Smuzhiyun reg = <0x50>; 295*4882a593Smuzhiyun pagesize = <32>; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun i2c-switch@73 { 299*4882a593Smuzhiyun compatible = "nxp,pca9546"; 300*4882a593Smuzhiyun #address-cells = <1>; 301*4882a593Smuzhiyun #size-cells = <0>; 302*4882a593Smuzhiyun reg = <0x73>; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun imux24: i2c@0 { 305*4882a593Smuzhiyun #address-cells = <1>; 306*4882a593Smuzhiyun #size-cells = <0>; 307*4882a593Smuzhiyun reg = <0>; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun imux25: i2c@1 { 311*4882a593Smuzhiyun #address-cells = <1>; 312*4882a593Smuzhiyun #size-cells = <0>; 313*4882a593Smuzhiyun reg = <1>; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun imux26: i2c@2 { 317*4882a593Smuzhiyun #address-cells = <1>; 318*4882a593Smuzhiyun #size-cells = <0>; 319*4882a593Smuzhiyun reg = <2>; 320*4882a593Smuzhiyun }; 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun imux27: i2c@3 { 323*4882a593Smuzhiyun #address-cells = <1>; 324*4882a593Smuzhiyun #size-cells = <0>; 325*4882a593Smuzhiyun reg = <3>; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun imux18: i2c@2 { 333*4882a593Smuzhiyun #address-cells = <1>; 334*4882a593Smuzhiyun #size-cells = <0>; 335*4882a593Smuzhiyun reg = <2>; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun ina230@45 { 338*4882a593Smuzhiyun compatible = "ti,ina230"; 339*4882a593Smuzhiyun reg = <0x45>; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun tmp421@48 { 343*4882a593Smuzhiyun compatible = "ti,tmp75"; 344*4882a593Smuzhiyun reg = <0x48>; 345*4882a593Smuzhiyun }; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun tmp421@49 { 348*4882a593Smuzhiyun compatible = "ti,tmp75"; 349*4882a593Smuzhiyun reg = <0x49>; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun eeprom@50 { 353*4882a593Smuzhiyun compatible = "atmel,24c64"; 354*4882a593Smuzhiyun reg = <0x50>; 355*4882a593Smuzhiyun pagesize = <32>; 356*4882a593Smuzhiyun }; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun i2c-switch@73 { 359*4882a593Smuzhiyun compatible = "nxp,pca9546"; 360*4882a593Smuzhiyun #address-cells = <1>; 361*4882a593Smuzhiyun #size-cells = <0>; 362*4882a593Smuzhiyun reg = <0x73>; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun imux28: i2c@0 { 365*4882a593Smuzhiyun #address-cells = <1>; 366*4882a593Smuzhiyun #size-cells = <0>; 367*4882a593Smuzhiyun reg = <0>; 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun imux29: i2c@1 { 371*4882a593Smuzhiyun #address-cells = <1>; 372*4882a593Smuzhiyun #size-cells = <0>; 373*4882a593Smuzhiyun reg = <1>; 374*4882a593Smuzhiyun }; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun imux30: i2c@2 { 377*4882a593Smuzhiyun #address-cells = <1>; 378*4882a593Smuzhiyun #size-cells = <0>; 379*4882a593Smuzhiyun reg = <2>; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun imux31: i2c@3 { 383*4882a593Smuzhiyun #address-cells = <1>; 384*4882a593Smuzhiyun #size-cells = <0>; 385*4882a593Smuzhiyun reg = <3>; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun imux19: i2c@3 { 393*4882a593Smuzhiyun #address-cells = <1>; 394*4882a593Smuzhiyun #size-cells = <0>; 395*4882a593Smuzhiyun reg = <3>; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun i2c-switch@40 { 398*4882a593Smuzhiyun compatible = "ti,ina230"; 399*4882a593Smuzhiyun reg = <0x40>; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun i2c-switch@41 { 403*4882a593Smuzhiyun compatible = "ti,ina230"; 404*4882a593Smuzhiyun reg = <0x41>; 405*4882a593Smuzhiyun }; 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun i2c-switch@45 { 408*4882a593Smuzhiyun compatible = "ti,ina230"; 409*4882a593Smuzhiyun reg = <0x45>; 410*4882a593Smuzhiyun }; 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun }; 415*4882a593Smuzhiyun}; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun&i2c2 { 418*4882a593Smuzhiyun status = "okay"; 419*4882a593Smuzhiyun // Mezz Management SMBus 420*4882a593Smuzhiyun}; 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun&i2c3 { 423*4882a593Smuzhiyun status = "okay"; 424*4882a593Smuzhiyun // SMBus to Board ID EEPROM 425*4882a593Smuzhiyun}; 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun&i2c4 { 428*4882a593Smuzhiyun status = "okay"; 429*4882a593Smuzhiyun // BMC Debug Header 430*4882a593Smuzhiyun ipmb0@10 { 431*4882a593Smuzhiyun compatible = "ipmb-dev"; 432*4882a593Smuzhiyun reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; 433*4882a593Smuzhiyun i2c-protocol; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun}; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun&i2c5 { 438*4882a593Smuzhiyun status = "okay"; 439*4882a593Smuzhiyun // CPU Voltage regulators 440*4882a593Smuzhiyun regulator@48 { 441*4882a593Smuzhiyun compatible = "infineon,pxe1610"; 442*4882a593Smuzhiyun reg = <0x48>; 443*4882a593Smuzhiyun }; 444*4882a593Smuzhiyun regulator@4a { 445*4882a593Smuzhiyun compatible = "infineon,pxe1610"; 446*4882a593Smuzhiyun reg = <0x4a>; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun regulator@50 { 449*4882a593Smuzhiyun compatible = "infineon,pxe1610"; 450*4882a593Smuzhiyun reg = <0x50>; 451*4882a593Smuzhiyun }; 452*4882a593Smuzhiyun regulator@52 { 453*4882a593Smuzhiyun compatible = "infineon,pxe1610"; 454*4882a593Smuzhiyun reg = <0x52>; 455*4882a593Smuzhiyun }; 456*4882a593Smuzhiyun regulator@58 { 457*4882a593Smuzhiyun compatible = "infineon,pxe1610"; 458*4882a593Smuzhiyun reg = <0x58>; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun regulator@5a { 461*4882a593Smuzhiyun compatible = "infineon,pxe1610"; 462*4882a593Smuzhiyun reg = <0x5a>; 463*4882a593Smuzhiyun }; 464*4882a593Smuzhiyun regulator@68 { 465*4882a593Smuzhiyun compatible = "infineon,pxe1610"; 466*4882a593Smuzhiyun reg = <0x68>; 467*4882a593Smuzhiyun }; 468*4882a593Smuzhiyun regulator@70 { 469*4882a593Smuzhiyun compatible = "infineon,pxe1610"; 470*4882a593Smuzhiyun reg = <0x70>; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun regulator@72 { 473*4882a593Smuzhiyun compatible = "infineon,pxe1610"; 474*4882a593Smuzhiyun reg = <0x72>; 475*4882a593Smuzhiyun }; 476*4882a593Smuzhiyun}; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun&i2c6 { 479*4882a593Smuzhiyun status = "okay"; 480*4882a593Smuzhiyun tpm@20 { 481*4882a593Smuzhiyun compatible = "infineon,slb9645tt"; 482*4882a593Smuzhiyun reg = <0x20>; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun tmp421@4e { 485*4882a593Smuzhiyun compatible = "ti,tmp421"; 486*4882a593Smuzhiyun reg = <0x4e>; 487*4882a593Smuzhiyun }; 488*4882a593Smuzhiyun tmp421@4f { 489*4882a593Smuzhiyun compatible = "ti,tmp421"; 490*4882a593Smuzhiyun reg = <0x4f>; 491*4882a593Smuzhiyun }; 492*4882a593Smuzhiyun eeprom@54 { 493*4882a593Smuzhiyun compatible = "atmel,24c64"; 494*4882a593Smuzhiyun reg = <0x54>; 495*4882a593Smuzhiyun pagesize = <32>; 496*4882a593Smuzhiyun }; 497*4882a593Smuzhiyun}; 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun&i2c7 { 500*4882a593Smuzhiyun status = "okay"; 501*4882a593Smuzhiyun //HSC, AirMax Conn A 502*4882a593Smuzhiyun}; 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun&i2c8 { 505*4882a593Smuzhiyun status = "okay"; 506*4882a593Smuzhiyun tmp421@1f { 507*4882a593Smuzhiyun compatible = "ti,tmp421"; 508*4882a593Smuzhiyun reg = <0x1f>; 509*4882a593Smuzhiyun }; 510*4882a593Smuzhiyun //Mezz Sensor SMBus 511*4882a593Smuzhiyun}; 512*4882a593Smuzhiyun 513*4882a593Smuzhiyun&i2c9 { 514*4882a593Smuzhiyun status = "okay"; 515*4882a593Smuzhiyun //USB Debug Connector 516*4882a593Smuzhiyun ipmb0@10 { 517*4882a593Smuzhiyun compatible = "ipmb-dev"; 518*4882a593Smuzhiyun reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; 519*4882a593Smuzhiyun i2c-protocol; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun}; 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun&pwm_tacho { 524*4882a593Smuzhiyun status = "okay"; 525*4882a593Smuzhiyun pinctrl-names = "default"; 526*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; 527*4882a593Smuzhiyun fan@0 { 528*4882a593Smuzhiyun reg = <0x00>; 529*4882a593Smuzhiyun aspeed,fan-tach-ch = /bits/ 8 <0x00>; 530*4882a593Smuzhiyun }; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun fan@1 { 533*4882a593Smuzhiyun reg = <0x01>; 534*4882a593Smuzhiyun aspeed,fan-tach-ch = /bits/ 8 <0x02>; 535*4882a593Smuzhiyun }; 536*4882a593Smuzhiyun}; 537