xref: /OK3568_Linux_fs/kernel/drivers/soc/aspeed/aspeed-lpc-ctrl.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright 2017 IBM Corporation
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
8*4882a593Smuzhiyun #include <linux/miscdevice.h>
9*4882a593Smuzhiyun #include <linux/mm.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/poll.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/aspeed-lpc-ctrl.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define DEVICE_NAME	"aspeed-lpc-ctrl"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define HICR5 0x0
21*4882a593Smuzhiyun #define HICR5_ENL2H	BIT(8)
22*4882a593Smuzhiyun #define HICR5_ENFWH	BIT(10)
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define HICR7 0x8
25*4882a593Smuzhiyun #define HICR8 0xc
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun struct aspeed_lpc_ctrl {
28*4882a593Smuzhiyun 	struct miscdevice	miscdev;
29*4882a593Smuzhiyun 	struct regmap		*regmap;
30*4882a593Smuzhiyun 	struct clk		*clk;
31*4882a593Smuzhiyun 	phys_addr_t		mem_base;
32*4882a593Smuzhiyun 	resource_size_t		mem_size;
33*4882a593Smuzhiyun 	u32		pnor_size;
34*4882a593Smuzhiyun 	u32		pnor_base;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun 
file_aspeed_lpc_ctrl(struct file * file)37*4882a593Smuzhiyun static struct aspeed_lpc_ctrl *file_aspeed_lpc_ctrl(struct file *file)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun 	return container_of(file->private_data, struct aspeed_lpc_ctrl,
40*4882a593Smuzhiyun 			miscdev);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun 
aspeed_lpc_ctrl_mmap(struct file * file,struct vm_area_struct * vma)43*4882a593Smuzhiyun static int aspeed_lpc_ctrl_mmap(struct file *file, struct vm_area_struct *vma)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun 	struct aspeed_lpc_ctrl *lpc_ctrl = file_aspeed_lpc_ctrl(file);
46*4882a593Smuzhiyun 	unsigned long vsize = vma->vm_end - vma->vm_start;
47*4882a593Smuzhiyun 	pgprot_t prot = vma->vm_page_prot;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT)
50*4882a593Smuzhiyun 		return -EINVAL;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	/* ast2400/2500 AHB accesses are not cache coherent */
53*4882a593Smuzhiyun 	prot = pgprot_noncached(prot);
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	if (remap_pfn_range(vma, vma->vm_start,
56*4882a593Smuzhiyun 		(lpc_ctrl->mem_base >> PAGE_SHIFT) + vma->vm_pgoff,
57*4882a593Smuzhiyun 		vsize, prot))
58*4882a593Smuzhiyun 		return -EAGAIN;
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	return 0;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun 
aspeed_lpc_ctrl_ioctl(struct file * file,unsigned int cmd,unsigned long param)63*4882a593Smuzhiyun static long aspeed_lpc_ctrl_ioctl(struct file *file, unsigned int cmd,
64*4882a593Smuzhiyun 		unsigned long param)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun 	struct aspeed_lpc_ctrl *lpc_ctrl = file_aspeed_lpc_ctrl(file);
67*4882a593Smuzhiyun 	struct device *dev = file->private_data;
68*4882a593Smuzhiyun 	void __user *p = (void __user *)param;
69*4882a593Smuzhiyun 	struct aspeed_lpc_ctrl_mapping map;
70*4882a593Smuzhiyun 	u32 addr;
71*4882a593Smuzhiyun 	u32 size;
72*4882a593Smuzhiyun 	long rc;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	if (copy_from_user(&map, p, sizeof(map)))
75*4882a593Smuzhiyun 		return -EFAULT;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	if (map.flags != 0)
78*4882a593Smuzhiyun 		return -EINVAL;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	switch (cmd) {
81*4882a593Smuzhiyun 	case ASPEED_LPC_CTRL_IOCTL_GET_SIZE:
82*4882a593Smuzhiyun 		/* The flash windows don't report their size */
83*4882a593Smuzhiyun 		if (map.window_type != ASPEED_LPC_CTRL_WINDOW_MEMORY)
84*4882a593Smuzhiyun 			return -EINVAL;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 		/* Support more than one window id in the future */
87*4882a593Smuzhiyun 		if (map.window_id != 0)
88*4882a593Smuzhiyun 			return -EINVAL;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 		/* If memory-region is not described in device tree */
91*4882a593Smuzhiyun 		if (!lpc_ctrl->mem_size) {
92*4882a593Smuzhiyun 			dev_dbg(dev, "Didn't find reserved memory\n");
93*4882a593Smuzhiyun 			return -ENXIO;
94*4882a593Smuzhiyun 		}
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 		map.size = lpc_ctrl->mem_size;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 		return copy_to_user(p, &map, sizeof(map)) ? -EFAULT : 0;
99*4882a593Smuzhiyun 	case ASPEED_LPC_CTRL_IOCTL_MAP:
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 		/*
102*4882a593Smuzhiyun 		 * The top half of HICR7 is the MSB of the BMC address of the
103*4882a593Smuzhiyun 		 * mapping.
104*4882a593Smuzhiyun 		 * The bottom half of HICR7 is the MSB of the HOST LPC
105*4882a593Smuzhiyun 		 * firmware space address of the mapping.
106*4882a593Smuzhiyun 		 *
107*4882a593Smuzhiyun 		 * The 1 bits in the top of half of HICR8 represent the bits
108*4882a593Smuzhiyun 		 * (in the requested address) that should be ignored and
109*4882a593Smuzhiyun 		 * replaced with those from the top half of HICR7.
110*4882a593Smuzhiyun 		 * The 1 bits in the bottom half of HICR8 represent the bits
111*4882a593Smuzhiyun 		 * (in the requested address) that should be kept and pass
112*4882a593Smuzhiyun 		 * into the BMC address space.
113*4882a593Smuzhiyun 		 */
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 		/*
116*4882a593Smuzhiyun 		 * It doesn't make sense to talk about a size or offset with
117*4882a593Smuzhiyun 		 * low 16 bits set. Both HICR7 and HICR8 talk about the top 16
118*4882a593Smuzhiyun 		 * bits of addresses and sizes.
119*4882a593Smuzhiyun 		 */
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 		if ((map.size & 0x0000ffff) || (map.offset & 0x0000ffff))
122*4882a593Smuzhiyun 			return -EINVAL;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 		/*
125*4882a593Smuzhiyun 		 * Because of the way the masks work in HICR8 offset has to
126*4882a593Smuzhiyun 		 * be a multiple of size.
127*4882a593Smuzhiyun 		 */
128*4882a593Smuzhiyun 		if (map.offset & (map.size - 1))
129*4882a593Smuzhiyun 			return -EINVAL;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 		if (map.window_type == ASPEED_LPC_CTRL_WINDOW_FLASH) {
132*4882a593Smuzhiyun 			if (!lpc_ctrl->pnor_size) {
133*4882a593Smuzhiyun 				dev_dbg(dev, "Didn't find host pnor flash\n");
134*4882a593Smuzhiyun 				return -ENXIO;
135*4882a593Smuzhiyun 			}
136*4882a593Smuzhiyun 			addr = lpc_ctrl->pnor_base;
137*4882a593Smuzhiyun 			size = lpc_ctrl->pnor_size;
138*4882a593Smuzhiyun 		} else if (map.window_type == ASPEED_LPC_CTRL_WINDOW_MEMORY) {
139*4882a593Smuzhiyun 			/* If memory-region is not described in device tree */
140*4882a593Smuzhiyun 			if (!lpc_ctrl->mem_size) {
141*4882a593Smuzhiyun 				dev_dbg(dev, "Didn't find reserved memory\n");
142*4882a593Smuzhiyun 				return -ENXIO;
143*4882a593Smuzhiyun 			}
144*4882a593Smuzhiyun 			addr = lpc_ctrl->mem_base;
145*4882a593Smuzhiyun 			size = lpc_ctrl->mem_size;
146*4882a593Smuzhiyun 		} else {
147*4882a593Smuzhiyun 			return -EINVAL;
148*4882a593Smuzhiyun 		}
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 		/* Check overflow first! */
151*4882a593Smuzhiyun 		if (map.offset + map.size < map.offset ||
152*4882a593Smuzhiyun 			map.offset + map.size > size)
153*4882a593Smuzhiyun 			return -EINVAL;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 		if (map.size == 0 || map.size > size)
156*4882a593Smuzhiyun 			return -EINVAL;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 		addr += map.offset;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 		/*
161*4882a593Smuzhiyun 		 * addr (host lpc address) is safe regardless of values. This
162*4882a593Smuzhiyun 		 * simply changes the address the host has to request on its
163*4882a593Smuzhiyun 		 * side of the LPC bus. This cannot impact the hosts own
164*4882a593Smuzhiyun 		 * memory space by surprise as LPC specific accessors are
165*4882a593Smuzhiyun 		 * required. The only strange thing that could be done is
166*4882a593Smuzhiyun 		 * setting the lower 16 bits but the shift takes care of that.
167*4882a593Smuzhiyun 		 */
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 		rc = regmap_write(lpc_ctrl->regmap, HICR7,
170*4882a593Smuzhiyun 				(addr | (map.addr >> 16)));
171*4882a593Smuzhiyun 		if (rc)
172*4882a593Smuzhiyun 			return rc;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 		rc = regmap_write(lpc_ctrl->regmap, HICR8,
175*4882a593Smuzhiyun 				(~(map.size - 1)) | ((map.size >> 16) - 1));
176*4882a593Smuzhiyun 		if (rc)
177*4882a593Smuzhiyun 			return rc;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 		/*
180*4882a593Smuzhiyun 		 * Enable LPC FHW cycles. This is required for the host to
181*4882a593Smuzhiyun 		 * access the regions specified.
182*4882a593Smuzhiyun 		 */
183*4882a593Smuzhiyun 		return regmap_update_bits(lpc_ctrl->regmap, HICR5,
184*4882a593Smuzhiyun 				HICR5_ENFWH | HICR5_ENL2H,
185*4882a593Smuzhiyun 				HICR5_ENFWH | HICR5_ENL2H);
186*4882a593Smuzhiyun 	}
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	return -EINVAL;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun static const struct file_operations aspeed_lpc_ctrl_fops = {
192*4882a593Smuzhiyun 	.owner		= THIS_MODULE,
193*4882a593Smuzhiyun 	.mmap		= aspeed_lpc_ctrl_mmap,
194*4882a593Smuzhiyun 	.unlocked_ioctl	= aspeed_lpc_ctrl_ioctl,
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun 
aspeed_lpc_ctrl_probe(struct platform_device * pdev)197*4882a593Smuzhiyun static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun 	struct aspeed_lpc_ctrl *lpc_ctrl;
200*4882a593Smuzhiyun 	struct device_node *node;
201*4882a593Smuzhiyun 	struct resource resm;
202*4882a593Smuzhiyun 	struct device *dev;
203*4882a593Smuzhiyun 	int rc;
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	dev = &pdev->dev;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	lpc_ctrl = devm_kzalloc(dev, sizeof(*lpc_ctrl), GFP_KERNEL);
208*4882a593Smuzhiyun 	if (!lpc_ctrl)
209*4882a593Smuzhiyun 		return -ENOMEM;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	/* If flash is described in device tree then store */
212*4882a593Smuzhiyun 	node = of_parse_phandle(dev->of_node, "flash", 0);
213*4882a593Smuzhiyun 	if (!node) {
214*4882a593Smuzhiyun 		dev_dbg(dev, "Didn't find host pnor flash node\n");
215*4882a593Smuzhiyun 	} else {
216*4882a593Smuzhiyun 		rc = of_address_to_resource(node, 1, &resm);
217*4882a593Smuzhiyun 		of_node_put(node);
218*4882a593Smuzhiyun 		if (rc) {
219*4882a593Smuzhiyun 			dev_err(dev, "Couldn't address to resource for flash\n");
220*4882a593Smuzhiyun 			return rc;
221*4882a593Smuzhiyun 		}
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 		lpc_ctrl->pnor_size = resource_size(&resm);
224*4882a593Smuzhiyun 		lpc_ctrl->pnor_base = resm.start;
225*4882a593Smuzhiyun 	}
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	dev_set_drvdata(&pdev->dev, lpc_ctrl);
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	/* If memory-region is described in device tree then store */
231*4882a593Smuzhiyun 	node = of_parse_phandle(dev->of_node, "memory-region", 0);
232*4882a593Smuzhiyun 	if (!node) {
233*4882a593Smuzhiyun 		dev_dbg(dev, "Didn't find reserved memory\n");
234*4882a593Smuzhiyun 	} else {
235*4882a593Smuzhiyun 		rc = of_address_to_resource(node, 0, &resm);
236*4882a593Smuzhiyun 		of_node_put(node);
237*4882a593Smuzhiyun 		if (rc) {
238*4882a593Smuzhiyun 			dev_err(dev, "Couldn't address to resource for reserved memory\n");
239*4882a593Smuzhiyun 			return -ENXIO;
240*4882a593Smuzhiyun 		}
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 		lpc_ctrl->mem_size = resource_size(&resm);
243*4882a593Smuzhiyun 		lpc_ctrl->mem_base = resm.start;
244*4882a593Smuzhiyun 	}
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	lpc_ctrl->regmap = syscon_node_to_regmap(
247*4882a593Smuzhiyun 			pdev->dev.parent->of_node);
248*4882a593Smuzhiyun 	if (IS_ERR(lpc_ctrl->regmap)) {
249*4882a593Smuzhiyun 		dev_err(dev, "Couldn't get regmap\n");
250*4882a593Smuzhiyun 		return -ENODEV;
251*4882a593Smuzhiyun 	}
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	lpc_ctrl->clk = devm_clk_get(dev, NULL);
254*4882a593Smuzhiyun 	if (IS_ERR(lpc_ctrl->clk))
255*4882a593Smuzhiyun 		return dev_err_probe(dev, PTR_ERR(lpc_ctrl->clk),
256*4882a593Smuzhiyun 				     "couldn't get clock\n");
257*4882a593Smuzhiyun 	rc = clk_prepare_enable(lpc_ctrl->clk);
258*4882a593Smuzhiyun 	if (rc) {
259*4882a593Smuzhiyun 		dev_err(dev, "couldn't enable clock\n");
260*4882a593Smuzhiyun 		return rc;
261*4882a593Smuzhiyun 	}
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	lpc_ctrl->miscdev.minor = MISC_DYNAMIC_MINOR;
264*4882a593Smuzhiyun 	lpc_ctrl->miscdev.name = DEVICE_NAME;
265*4882a593Smuzhiyun 	lpc_ctrl->miscdev.fops = &aspeed_lpc_ctrl_fops;
266*4882a593Smuzhiyun 	lpc_ctrl->miscdev.parent = dev;
267*4882a593Smuzhiyun 	rc = misc_register(&lpc_ctrl->miscdev);
268*4882a593Smuzhiyun 	if (rc) {
269*4882a593Smuzhiyun 		dev_err(dev, "Unable to register device\n");
270*4882a593Smuzhiyun 		goto err;
271*4882a593Smuzhiyun 	}
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	return 0;
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun err:
276*4882a593Smuzhiyun 	clk_disable_unprepare(lpc_ctrl->clk);
277*4882a593Smuzhiyun 	return rc;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun 
aspeed_lpc_ctrl_remove(struct platform_device * pdev)280*4882a593Smuzhiyun static int aspeed_lpc_ctrl_remove(struct platform_device *pdev)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun 	struct aspeed_lpc_ctrl *lpc_ctrl = dev_get_drvdata(&pdev->dev);
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	misc_deregister(&lpc_ctrl->miscdev);
285*4882a593Smuzhiyun 	clk_disable_unprepare(lpc_ctrl->clk);
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	return 0;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun static const struct of_device_id aspeed_lpc_ctrl_match[] = {
291*4882a593Smuzhiyun 	{ .compatible = "aspeed,ast2400-lpc-ctrl" },
292*4882a593Smuzhiyun 	{ .compatible = "aspeed,ast2500-lpc-ctrl" },
293*4882a593Smuzhiyun 	{ },
294*4882a593Smuzhiyun };
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun static struct platform_driver aspeed_lpc_ctrl_driver = {
297*4882a593Smuzhiyun 	.driver = {
298*4882a593Smuzhiyun 		.name		= DEVICE_NAME,
299*4882a593Smuzhiyun 		.of_match_table = aspeed_lpc_ctrl_match,
300*4882a593Smuzhiyun 	},
301*4882a593Smuzhiyun 	.probe = aspeed_lpc_ctrl_probe,
302*4882a593Smuzhiyun 	.remove = aspeed_lpc_ctrl_remove,
303*4882a593Smuzhiyun };
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun module_platform_driver(aspeed_lpc_ctrl_driver);
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, aspeed_lpc_ctrl_match);
308*4882a593Smuzhiyun MODULE_LICENSE("GPL");
309*4882a593Smuzhiyun MODULE_AUTHOR("Cyril Bur <cyrilbur@gmail.com>");
310*4882a593Smuzhiyun MODULE_DESCRIPTION("Control for aspeed 2400/2500 LPC HOST to BMC mappings");
311